MICRO-34 Advance Program
Saturday, December 1, 2001
Tutorials/Workshops
Sunday, December 2, 2001
Tutorials/Workshops
Monday, December 3, 2001
Welcome and Keynote I
8:40am-10:00am, Monday December 3
Welcome
8:40am-9:00am
- Yale Patt, General Chair
- Josh Fisher and Paolo Faraboschi, Program Co-chairs
Keynote I
9:00am-10:00am
Break
10:00am-10:30am
Session 1: Novel Ideas
10:30am-12:30pm, Monday December 3
- Skipper: A Microarchitecture for Exploiting Control-Flow Independence
Chen-yong Cher and T.N. Vijaykumar (Purdue University)
- Performing Dynamic Optimizations using the rePLay Microarchitecture
Brian Fahs, Satarupa Bose, Matthew Crum, Gregory Muthler, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, and Steven S. Lumetta (University of Illinois at Urbana-Champaign)
- Using Variable-MHz Microprocessors to Efficiently Handle Uncertainty in Real-Time Systems
Eric Rotenberg (North Carolina State University)
- A Design Space Evaluation of Grid Processor Architectures
Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, and Stephen W. Keckler (University of Texas at Austin)
Lunch
12:30am-2:00pm
Session 2: Memory Hierarchies
2:00pm-3:30pm, Monday December 3
- Reducing Set-Associative Cache Energy via Selective Direct-Mapping
Michael D. Powell, Amit Agrawal, T.N. Vijaykumar, Babak Falsafi, and Kaushik Roy (Purdue University)
- A Code Decompression Architecture for VLIW Processors
Yuan Xie, Haris Lekatsas, and Wayne Wolf
(Princeton University)
- Direct Load: Hiding Memory Latency with Accurate Prior Resolution of Cache Coordinates
Byung-Kwon Chung (Sun Microsystems), Jinsuo Zhang, Jih-Kwon Peir (University of Florida), Shih-Chang Lai (Oregon State University), and Konrad Lai (Intel Corporation)
Break
3:30pm-4:00pm
Session 3: Energy Efficient Architectures
4:00pm-6:00pm, Monday December 3
- Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources
Dmitry V. Ponomarev, Gurhan Kucuk, and Kanad Ghose (SUNY Binghamton)
- Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy
W. Zhang, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, D. Duarte, and Y-T. Fai (Pennsylvania State University)
- Reducing Power with Dynamic Critical Path Information
John S. Seng, Eric S. Tune, and Dean M. Tullsen (University of California, San Diego)
- Direct Addressed Caches for Reduced Power Consumption
Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanovic (MIT)
Tuesday, December 4, 2001
Keynote II
9:00am-10:00am
Break
10:00am-10:30am
Session 5: Modulo Scheduling
10:30am-12:00pm, Tuesday December 4
Lunch
12:00pm-1:30pm
Session 6: Compilation
1:30pm-3:00pm, Tuesday December 4
Break
3:00pm-3:30pm
Session 7: Superscalar Architectures
3:30pm-5:30pm, Tuesday December 4
Panel
5:30pm-7:00pm
Business Meeting
7:00pm-8:00pm
Wednesday, December 5, 2001
Session 8: Multimedia and Graphics
8:30am-10:30am, Wednesday December 5
- Saving Energy with Architectural and Frequency Adaptations for Multimedia Applications
Christopher J. Hughes, Jayanth Srinivasan, and Sarita V. Adve (University of Illinois at Urbana-Champaign)
- Enhancing Loop Buffering of Media and Telecommunications Applications Using Low-Overhead Predication
John W. Sias, Hillery C. Hunter, and Wen-mei W. Hwu (University of Illinois at Urbana-Champaign)
- Cool-Cache for Hot Multimedia
Osman S. Unsal, Raksit Ashok, Israel Koren, C.M. Krishna, and Csaba Andras Moritz(University of Massachusetts at Amherst)
- Zone Rendering: A Technology for Competitive 3D Performance in Low-Cost PC Systems
Emile Hsieh, Vladimir Pentkovski, and Tom Piazza (Intel Corporation)
Break
10:30am-11:00am
Session 9: Multithreading and Value Prediction
11:00am-1:00pm, Wednesday December 5