Micro-37 Web Page

December 6th

8:15-8:30	Welcome
8:30-9:30	Keynote 1 Chair: John Shen, Intel Corporation Microarchitecture and Design Challenges for Gigascale Integration (slides) Shekhar Borkar, Intel Corporation
9:30-10:00	Break
10:00-11:30	Session 1: Instruction Collapsing Chair: Dean Tullsen, UC San Diego • Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication (slides) Peter G. Sassone, Georgia Institute of Technology D. Scott Wills, Georgia Institute of Technology • Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth Anne Bracy, Univeristy of Pennsylvania Prashant Prahlad, Univeristy of Pennsylvania Amir Roth, Univeristy of Pennsylvania • Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization (slides) Nathan Clark, University of Michigan Manjunath Kudlur, University of Michigan Hyunchul Park, University of Michigan Scott Mahlke, University of Michigan Krisztian Flautner, ARM Ltd.
11:30-13:00	Lunch break
13:00-14:30	Session 2: Performance Evaluation Chair: Pradip Bose, IBM • Microlib: A Case for the Quantitative Comparison of Micro-Architecture Mechanims Daniel Gracia Pérez, Paris Sud University, France Gilles Mouchard, Paris Sud University, France Olivier Temam, Paris Sud University, France • Automatic Synthesis of High-Speed Microprocessor Simulators (slides) Martin Burtscher, Cornell University Ilya Ganusov, Cornell University • Thermal Modeling, Characterization and Management of On-chip Networks Li Shang, Princeton University Li-Shiuan Peh, Princeton University Niraj K. Jha, Princeton University Amit Kumar, Princeton University
14:30-15:00	Break
15:00-16:30	Session 3: Trace Analysis Chair: David Kaeli, Northeastern University • Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation (slides) (more info) Harish Patil, Intel Corporation Robert Cohn, Intel Corporation Mark Charney, Intel Corporation Rajiv Kapoor, Intel Corporation Andrew Sun, Intel Corporation Anand Karunanidhi, Intel Corporation • The Fuzzy Correlation between Code and Performance Predictability (slides) Murali Annavaram, Intel Corporation Ryan Rakvic, Intel Corporation Marzia Polito, Intel Corporation Richard Hankins, Intel Corporation Jean-Yves Bouguet, Intel Corporation Bob Davies, Intel Corporation • Whole Execution Traces Xiangyu Zhang, University of Arizona Rajiv Gupta, University of Arizona
16:30 - 17:00	Break
17:00 - 18:00	Session 4: Control Flow Chair: Doug Burger, University of Texas at Austin • Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery David N. Armstrong, University of Texas at Austin Hyesoon Kim, University of Texas at Austin Onur Mutlu, University of Texas at Austin Yale N. Patt, University of Texas at Austin • Control flow optimizations through dynamic reconvergence prediction Jamison Collins, UC San Diego Dean Tullsen, UC San Diego

December 7th

8:00-9:00	Keynote 2 Chair: Antonio González, UPC-Intel Labs Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation (slides) Guri Sohi, Computer Sciences Department, University of Wisconsin-Madison
9:00 - 10:00	Session 5: Adaptive Microarchitectures Chair: Babak Falsafi, Carnegie Mellon University • A Case for Clumsy Packet Processors (slides) Arindam Mallik, Northwestern University Gokhan Memik, Northwestern University • Dynamically Trading Frequency for Complexity in a GALS Microprocessor (slides) Steven Dropsho, University of Rochester Greg Semeraro, Rochester Institute of Technology David H. Albonesi, University of Rochester Grigorios Magklis, University of Rochester Michael L. Scott, University of Rochester
10:00 - 10:30	Break
10:30 - 12:00	Session 6: Multithreaded/Multicore Processors Chair: Josep Torrellas, UIUC • Dynamically Controlled Resource Allocation in SMT Processors Francisco J. Cazorla, UPC Enrique Fernandez, University of Las Palmas de Gran Canaria Alex Ramirez, UPC Mateo Valero, UPC • Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy Eric Tune, UC San Diego Rakesh Kumar, UC San Diego Dean M. Tullsen, UC San Diego Brad Calder, UC San Diego • Conjoined-core chip multiprocessing Rakesh Kumar, UC San Diego Norman P. Jouppi, HP Labs Dean Tullsen, UC San Diego
12:00 - 13:00	Lunch break
13:00 - 15:00	Session 7: Security Chair: Yale Patt, University of Texas at Austin • Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow Nathan Tuck, UC San Diego Brad Calder, UC San Diego George Varghese, UC San Diego • Minos: Control Data Attack Prevention Orthogonal to Memory Model (slides) Jedidiah R. Crandall, UC Davis Frederic T. Chong, UC Davis • A Hardware-Software Platform for Intrusion Prevention Darko Kirovski, Microsoft Research Milenko Drinic, Microsoft Research • RIFLE: An Architectural Framework for User-Centric Information-Flow Security (slides) Neil Vachharajani - Princeton University Matthew J. Bridges - Princeton University George Reis - Princeton University Ram Rangan - Princeton University Jason A. Blome - Princeton University Jonathan Chang - Princeton University Guilherme Ottoni - Princeton University Manish Vachharajani - Princeton University David I. August - Princeton University

December 8th

9:00 - 10:00	Session 8: Reliability Chair: Rajiv Gupta, University of Arizona • Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures Jared C. Smolens, Carnegie Mellon University Jangwoo Kim, Carnegie Mellon University James C. Hoe, Carnegie Mellon University Babak Falsafi, Carnegie Mellon University • AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-based Invariants (slides) Pin Zhou, UIUC Wei Liu, UIUC Long Fei, Purdue University Feng Qin, UIUC Shan Lu, UIUC Yuanyuan Zhou, UIUC Sam Midkiff, Purdue University Josep Torrellas, UIUC
10:00 - 10:30	Break
10:30 - 12:00	Session 9: Code Generation and Optimization Chair: Jim Dehnert, Transmeta • Optimal Superblock Scheduling Using Enumeration (slides) Ghassan Shobaki, UC Davis Kent Wilken, UC Davis • Compiler optimization for Transaction Processing workloads on Itanium Linux systems Gerolf Hoflehner, Intel Corporation Rod Skinner, Intel Corporation Yong-fong Lee, Intel Corporation Wei Li, Intel Corporation Knud Kirkegaard, Intel Corporation Dan Lavery, Intel Corporation • Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure (slides) Oguz Ergin, State University of New York at Binghamton Deniz Balkan, State University of New York at Binghamton Kanad Ghose, State University of New York at Binghamton Dmitry Ponomarev, State University of New York at Binghamton
12:00 - 13:00	Lunch Break
13:00 - 15:00	Session 10: Caches and Memory Chair: Scott Mahlke, University of Michigan • Managing Wire Delay in Large Chip-Multiprocessor Caches (slides) Bradford M. Beckmann, University of Wisconsin-Madison David A. Wood, University of Wisconsin-Madison • Cache Refill/Access Decoupling for Vector Machines (slides) Christopher Batten, Massachusetts Institute of Technology Ronny Krashinsky, Massachusetts Institute of Technology Steve Gerding, Massachusetts Institute of Technology Krste Asanovic, Massachusetts Institute of Technology • Adaptive History-Based Memory Schedulers (slides) Ibrahim Hur, University of Texas at Austin & IBM Austin Calvin Lin, University of Texas at Austin • Memory Controller Optimizations for Web Servers Scott Rixner, Rice University