The 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015

Conference is at the Tapa tower, second floor

Schedule

Dec. 6 (Sun.)

06:00pm | 08:00pm

Reception
Room: Tapa Ballroom 1

Dec. 7 (Mon.)

07:00am \| 08:00am	Breakfast (continues until 9am) Room: Palace Lounge (In front of Tapa Ballroom 1)
08:00am \| 08:20am	Opening Room: Tapa Ballroom 2
	Prof. Milos Prvulovic (General Chair), Prof. Moinuddin Qureshi (Program Chair) Message from the General Chair: PDF Message from the Program Chair: PDF
08:20am \| 09:20am	Keynote Room: Tapa Ballroom 2 Session Chair: Moinuddin Qureshi
	"The Human Intranet - Where Swarms and Humans Meet" - Prof. Jan Rabaey (UC Berkeley) (slides)
09:20am \| 10:20am	Best Paper Candidates Room: Tapa Ballroom 2 Session Chair: Joel Emer
	Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways? (slides) Binh Pham (Rutgers University), Jan Vesely (Rutgers University), Gabriel H. Loh (AMD Research), Abhishek Bhattacharjee (Rutgers University) Exploiting Commutativity to Reduce the Cost of Updates to Shared Data in Cache-Coherent Systems (slides) Guowei Zhang (Massachusetts Institute of Technology), Webb Horn (Massachusetts Institute of Technology), Daniel Sanchez (Massachusetts Institute of Technology) CCICheck: Using μhb Graphs to Verify the Coherence-Consistency Interface (slides) Yatin A. Manerkar (Princeton University), Daniel Lustig (Princeton University), Michael Pellauer (NVIDIA), Margaret Martonosi (Princeton University)
10:20am \| 10:40am	Break
10:40am \| 12:00pm	Lightning Session Room: Tapa Ballroom 2 Session Chair: Onur Mutlu
12:00pm \| 02:00pm	Lunch Room: Tapa Ballroom 1
02:00pm \| 03:20pm	Cache [Session A1] Room: Tapa Ballroom 2 Session Chair: Chris Wilkerson	Security [Session A2] Room: Honolulu Suite Session Chair: Edward Suh
	HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods (slides) Angelos Arelakis (Chalmers University of Technology), Fredrik Dahlgren (Chalmers University of Technology), Per Stenstrom (Chalmers University of Technology) Doppelganger: A Cache for Approximate Computing (slides) Joshua San Miguel (University of Toronto), Jorge Albericio (University of Toronto), Andreas Moshovos (University of Toronto), Natalie Enright Jerger (University of Toronto) The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-Application Interference at Shared Caches and Main Memory Lavanya Subramanian (Intel Labs), Vivek Seshadri (Carnegie Mellon University), Arnab Ghosh (IIT Kanpur), Samira Khan (University of Virginia), Onur Mutlu (Carnegie Mellon University) MORC: A Manycore-Oriented Compressed Cache (slides) Tri M. Nguyen (Princeton University), David Wentzlaff (Princeton University)	Avoiding Information Leakage in the Memory Controller with Fixed Service Policies (slides) Ali Shafiee (University of Utah), Akhila Gundu (University of Utah), Manjunath Shevgoor (University of Utah), Rajeev Balasubramonian (University of Utah), Mohit Tiwari (University of Texas) Austin" Fork Path: Improving Efficiency of ORAM by Removing Redundant Memory Accesses Xian Zhang (Peking University), Guangyu Sun (Peking University), Chao Zhang (Peking University), Weiqi Zhang (Peking University), Yun Liang (Peking University), Tao Wang (Peking University), Yiran Chen (University of Pittsburgh), Jia Di (University of Arkansas) Locking Down Insecure Indirection with Hardware-Based Control-Data Isolation (slides) William Arthur (University of Michigan), Sahil Madeka (University of Michigan), Reetuparna Das (University of Michigan), Todd Austin (University of Michigan) Authenticache: Harnessing Cache ECC for System Authentication (slides) Anys Bacha (The Ohio State University), Radu Teodorescu (The Ohio State University)
03:20pm \| 03:40pm	Break
03:40pm \| 05:00pm	Prefetching [Session B1] Room: Tapa Ballroom 2 Session Chair: Aamer Jaleel	Concurrency [Session B2] Room: Honolulu Suite Session Chair: Nam Sung Kim
	Efficiently Prefetching Complex Address Patterns (slides) Manjunath Shevgoor (University of Utah), Sahil Koladiya (University of Utah), Rajeev Balasubramonian (University of Utah), Chris Wilkerson (Intel Labs), Seth Pugsley (Intel Labs), Zeshan Chishti (Intel Labs) Self-Contained, Accurate Precomputation Prefetching (slides) Islam Atta (University of Toronto), Xin Tong (University of Toronto), Vijayalakshmi Srinivasan (IBM), Ioana Baldini (IBM), Andreas Moshovos (University of Toronto) Confluence: Unified Instruction Supply for Scale-Out Servers Cansu Kaynak (EcoCloud, EPFL), Boris Grot (University of Edinburgh), Babak Falsafi (EcoCloud, EPFL) IMP: Indirect Memory Prefetcher (slides) Xiangyao Yu (MIT), Christopher J. Hughes (Intel Labs), Nadathur Satish (Intel Labs), Srinivas Devadas (MIT)	DeSC: Decoupled Supply-Compute Communication Management for Heterogeneous Architectures (slides) Tae Jun Ham (Princeton University), Juan Luis Aragon (University of Murcia), Margaret Martonosi (Princeton University) Efficient Warp Execution in Presence of Divergence with Collaborative Context Collection Farzad Khorasani (University of California Riverside), Rajiv Gupta (University of California Riverside), Laxmi N. Bhuyan (University of California Riverside) Control Flow Coalescing on a Hybrid Dataflow/von Neumann GPGPU (slides) Dani Voitsechov (Technion), Yoav Etsion (Technion) A Scalable Architecture for Ordered Parallelism (slides) Mark C. Jeffrey (Massachusetts Institute of Technology), Suvinay Subramanian (Massachusetts Institute of Technology), Cong Yan (Massachusetts Institute of Technology), Joel Emer (Massachusetts Institute of Technology / NVIDIA), Daniel Sanchez (Massachusetts Institute of Technology)
05:00pm \| 05:30pm	(Nothing)
05:30pm \| 06:00pm	Program Chair Experience Report (ppt) Room: Tapa Ballroom 2
06:00pm \| 08:00pm	Drinks and Business Meeting Room: Tapa Ballroom 2

Dec. 8 (Tue.)

07:00am \| 08:00am	Breakfast (continues until 9am) Room: Palace Lounge (In front of Tapa Ballroom 1)
08:00am \| 09:00am	Keynote II Room: Tapa Ballroom 2 Session Chair: Trevor Mudge
	"Preparing for a Post Moore's Law World" - Prof. Todd Austin (U Michigan) (slides)
09:00am \| 10:00am	DRAM [Session C1] Room: Tapa Ballroom 2 Session Chair: Daniel Sanchez	Voltage [Session C2] Room: Honolulu Suite Session Chair: Murali Annavaram
	More is Less: Improving the Energy Efficiency of Data Movement via Opportunistic Use of Sparse Codes Yanwei Song (University of Rochester), Engin Ipek (University of Rochester) Improving DRAM Latency with Dynamic Asymmetric Subarray Shih-Lien Lu (Intel), Ying-Chen Lin (National Taiwan University), Chia-Lin Yang (National Taiwan University) Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses (slides) Vivek Seshadri (Carnegie Mellon University), Thomas Mullins (Carnegie Mellon University), Amirali Boroumand (Carnegie Mellon University), Onur Mutlu (Carnegie Mellon University), Phillip B. Gibbons (Carnegie Mellon University), Michael A. Kozuch (Intel Pittsburgh), Todd C. Mowry (Carnegie Mellon University)	The CRISP Performance Model for Dynamic Voltage and Frequency Scaling in a GPGPU (slides) Rajib Nath (UCSD), Dean Tullsen (UCSD) Safe Limits on Voltage Reduction Efficiency in GPUs: a Direct Measurement Approach (slides) Jingwen Leng (University of Texas at Austin / IBM T.J. Watson Research), Alper Buyuktosunoglu (IBM T.J. Watson Research), Ramon Bertran (IBM T.J. Watson Research), Pradip Bose (IBM T.J. Watson Research), Vijay Janapa Reddi (University of Texas at Austin) Adaptive Guardband Scheduling to Improve System-level Efficiency of POWER7+ (slides) Yazhou Zu (UT Austin), Charles R. Lefurgy (IBM), Jingwen Leng (UT Austin), Matthew Halpern (UT Austin), Michael S. Floyd (IBM), Vijay Janapa Reddi (UT Austin)
10:00am \| 10:20am	Break
10:20am \| 12:00pm	Micro-architecture [Session D1] Room: Tapa Ballroom 2 Session Chair: Uri Weiser	GPU [Session D2] Room: Honolulu Suite Session Chair: Tor Aamodt
	DynaMOS: Dynamic Schedule Migration for Heterogeneous Cores (slides) Shruti Padmanabha (University of Michigan), Andrew Lukefahr (University of Michigan), Reetuparna Das (University of Michigan), Scott Mahlke (University of Michigan) Long Term Parking: Criticality-aware Resource Allocation in OOO Processors Andreas Sembrant (Uppsala University), Trevor E. Carlson (Uppsala University), Erik Hagersten (Uppsala University), David Black-Schaffer (Uppsala University), Arthur Perais (IRISA/INRIA), Andre Seznec (IRISA/INRIA), Pierre Michaud (IRISA/INRIA) The Inner Most Loop Iteration counter: a new dimension in branch history (slides) Andre Seznec (INRIA/IRISA), Joshua San Miguel (University of Toronto), Jorge Albericio (University of Toronto) Filtered Runahead Execution with a Runahead Buffer (slides) Milad Hashemi (UT Austin), Yale N. Patt (UT Austin) Bungee Jumps: Accelerating Indirect Branches Through HW/SW Co-Design (slides) Daniel S. McFarlin (Carnegie Mellon University), Craig Zilles (University of Illinois, Urbana-Champaign)	SAWS: Synchronization Aware GPGPU Warp Scheduling for Multiple Independent Warp Schedulers Jiwei Liu (University of Pittsburgh), Jun Yang (University of Pittsburgh), Rami Melhem (University of Pittsburgh) Enabling Coordinated Register Allocation and Thread-level Parallelism Optimization for GPUs Xiaolong Xie (Center for Energy-Efficient Computing and Applications, Peking University), Yun Liang (Center for Energy-Efficient Computing and Applications, Peking University), Xiuhong Li (Center for Energy-Efficient Computing and Applications, Peking University), Yudong Wu (Center for Energy-Efficient Computing and Applications, Peking University), Guangyu Sun (Center for Energy-Efficient Computing and Applications, Peking University), Tao Wang (Center for Energy-Efficient Computing and Applications, Peking University), Dongrui Fan (Institute of Computing Technology (ICT) Chinese Academy of Sciences) Free Launch: Optimizing GPU Dynamic Kernel Launches through Thread Reuse Guoyang Chen (North Carolina State University), Xipeng Shen (North Carolina State University) GPU Register File Virtualization (slides) Hyeran Jeon (San Jose State University), Gokul Subramanian Ravi (University of Wisconsin-Madison), Nam Sung Kim (University of Illinois, Urbana-Champaign), Murali Annavaram (University of Southern California) WarpPool: Sharing Requests with Inter-Warp Coalescing for Throughput Processors (slides) John Kloosterman (University of Michigan), Jonathan Beaumont (University of Michigan), Mick Wollman (University of Michigan), Ankit Sethia (University of Michigan), Ron Dreslinski (University of Michigan), Trevor Mudge (University of Michigan), Scott Mahlke (University of Michigan)
12:00pm \| 02:00pm	Lunch (Awards) Room: Tapa Ballroom 1
02:00pm \| 03:40pm	Accelerator [Session E1] Room: Tapa Ballroom 2 Session Chair: Babak Falsafi	Mobile & Emerging Systems [Session E2] Room: Honolulu Suite Session Chair: Vijay Janapa Reddi
	Ultra-Low Power Render-Based Collision Detection for CPU/GPU Systems (slides) Enrique de Lucas (Polytechnic University of Catalonia), Pedro Marcuello (Broadcom Corporation), Joan-Manuel Parcerisa (Polytechnic University of Catalonia), Antonio Gonzalez (Polytechnic University of Catalonia) Execution Time Prediction for Energy-Efficient Hardware Accelerators (slides) Tao Chen (Cornell University), Alexander Rucker (Cornell University), G. Edward Suh (Cornell University) Border Control: Sandboxing Accelerators (slides) Lena E. Olson (University of Wisconsin-Madison), Jason Power (University of Wisconsin-Madison), Mark D. Hill (University of Wisconsin-Madison), David A. Wood (University of Wisconsin-Madison) Neural Acceleration for GPU Throughput Processors (slides) (slides) Amir Yazdanbakhsh (Georgia Institute of Technology), Jongse Park (Georgia Institute of Technology), Hardik Sharma (Georgia Institute of Technology), Pejman Lotfi-Kamran (Institute for Research in Fundamental Sciences (IPM)), Hadi Esmaeilzadeh (Georgia Institute of Technology) Neuromorphic Accelerators: A Comparison Between Neuroscience and Machine-Learning Approaches Zidong Du (State Key Laboratory of Computer Architecture (CARCH), ICT, CAS, China), Daniel D Ben-Dayan Rubin (Intel Labs, Israel), Yunji Chen (State Key Laboratory of Computer Architecture (CARCH), ICT, CAS, China), Liqiang He (College of Computer Science, Inner Mongolia University, China), Tianshi Chen (State Key Laboratory of Computer Architecture (CARCH), ICT, CAS, China), Lei Zhang (University of Science and Technology of China), Chengyong Wu (State Key Laboratory of Computer Architecture (CARCH), ICT, CAS, China), Olivier Temam (Inria, France)	Prediction-Guided Performance-Energy Trade-off for Interactive Applications (slides) Daniel Lo (Cornell University), Taejoon Song (Cornell University), G. Edward Suh (Cornell University) Architecture-aware Automatic Computation Offload for Native Applications (slides) Gwangmu Lee (POSTECH), Hyunjoon Park (POSTECH), Seonyeong Heo (POSTECH), Kyung-Ah Chang (Samsung Electronics), Hyogun Lee (Samsung Electronics), Hanjun Kim (POSTECH) Fast Support for Unstructured Data Processing: the Unified Automata Processor (slides) Yuanwei Fang (University of Chicago), Tung T. Hoang (University of Chicago), Michela Becchi (University of Missouri), Andrew A. Chien (University of Chicago) Enabling Interposer-based Disintegration of Multi-core Processors Ajaykumar Kannan (University of Toronto), Natalie Enright Jerger (University of Toronto), Gabriel H. Loh (AMD Research) DCS: A Fast and Scalable Device-Centric Server Architecture (slides) Jaehyung Ahn (POSTECH), Dongup Kwon (POSTECH), Youngsok Kim (POSTECH), Mohammadamin Ajdari (POSTECH), Jaewon Lee (POSTECH), Jangwoo Kim (POSTECH)
03:40pm \| 04:00pm	Break
04:00pm \| 05:30pm	Posters Room: Palace Lounge
05:30pm \| 06:00pm	(Nothing)
06:00pm \| 09:00pm	Luau Location: Great Lawn

Dec. 9 (Wed.)

07:00am \| 08:00am	Breakfast (continues until 9am) Room: Palace Lounge
08:00am \| 09:00am	Keynote III Room: Tapa Ballroom 2 Session Chair: Shih-Lien Lu
	"Future Processor/Memory System Architecture" - J. Thomas Pawlowski (Micron) (slides)
09:00am \| 10:00am	Datacenter [Session F1] Room: Tapa Ballroom 2 Session Chair: Mike Ferdman	Memory Systems [Session F2] Room: Honolulu Suite Session Chair: Andre Seznec
	Modeling the Implications of DRAM Failures and Protection Techniques on Datacenter TCO (slides) Panagiota Nikolaou (University of Cyprus), Yiannakis Sazeides (University of Cyprus), Lorena Ndreu (University of Cyprus), Marios Kleanthous (MAP S.Platis) TimeTrader: Exploiting Latency Tail to Save Datacenter Energy for Online Search (slides) Balajee Vamanan (Purdue University), Hamza Bin Sohail (Purdue University), Jahangir Hasan (Google Inc.), T. N. Vijaykumar (Purdue University) Rubik: Fast Analytical Power Management for Latency-Critical Systems (slides) Harshad Kasture (MIT), Davide B. Bartolini (MIT), Nathan Beckmann (MIT), Daniel Sanchez (MIT)	CLEAN-ECC: High Reliablity ECC for Adaptive Granularity Memory System Seong-Lyong Gong (UT Austin), Minsoo Rhu (NVIDIA Research), Jungrae Kim (UT Austin), Jinsuk Chung (UT Austin), Mattan Erez (UT Austin) vCache: Architectural Support for Transparent and Isolated Virtual LLCs in Virtualized Environments (slides) Daehoon Kim (University of Illinois, Urbana-Champaign), Hwanju Kim (University of Cambridge), Nam Sung Kim (University of Illinois, Urbana-Champaign), Jaehyuk Huh (KAIST) An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors (slides) Kathryn E. Gray (University of Cambridge), Gabriel Kerneis (University of Cambridge), Dominic Mulligan (University of Cambridge), Christopher Pulte (University of Cambridge), Susmit Sarkar ( University of St Andrews), Peter Sewell (University of Cambridge)
10:00am \| 10:20am	Break
10:20am \| 12:00pm	Coherence, Consistency, Persistency [Session G1] Room: Tapa Ballroom 2 Session Chair: Thomas Wenisch	Modeling & Characterisation [Session G2] Room: Honolulu Suite Session Chair: Hsien-Hsin Lee
	Efficient GPU Synchronization without Scopes: Saying No to Complex Consistency Models (slides) Matthew D. Sinclair (University of Illinois at Urbana-Champaign), Johnathan Alsop (University of Illinois at Urbana-Champaign), Sarita V. Adve (University of Illinois at Urbana-Champaign) Efficient Persist Barriers for Multicores (slides) Arpit Joshi (University of Edinburgh), Vijay Nagarajan (University of Edinburgh), Marcelo Cintra (Intel), Stratis Viglas (University of Edinburgh) ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems (slides) Jinglei Ren (Tsinghua University), Jishen Zhao (University of California, Santa Cruz), Samira Khan (University of Virginia), Jongmoo Choi (Dankook University), Yongwei Wu (Tsinghua University), Onur Mutlu (Carnegie Mellon University) Coherence Domain Restriction on Large Scale Systems Yaosheng Fu (Princeton University), Tri M. Nguyen (Princeton University), David Wentzlaff (Princeton University) Efficiently Enforcing Strong Memory Ordering in GPUs (slides) Abhayendra Singh (University of Michigan, Ann Arbor), Shaizeen Aga (University of Michigan, Ann Arbor), Satish Narayanasamy (University of Michigan, Ann Arbor)	Characterizing, Modeling, and Improving the QoE of Mobile Devices with Low Battery Level Kaige Yan (University of Houston), Xingyao Zhang (University of Houston), Xin Fu (University of Houston) Cross-Architecture Performance Prediction (XAPP) Using CPU Code to Predict GPU Performance (slides) Newsha Ardalani (University of Wisconsin, Madison), Clint Lestourgeon (University of Wisconsin, Madison), Karthikeyan Sankaralingam (University of Wisconsin, Madison), Xiaojin Zhu (University of Wisconsin, Madison) A Fast and Accurate Analytical Technique to Compute the AVF of Sequential Bits in a Processor Steven Raasch (Intel), Arijit Biswas (Intel), Jon Stephan (Intel), Paul Racunas (Nvidia), Joel Emer (Nvidia) Enabling Portable Energy Efficiency with Memory Accelerated Library Qi Guo (Carnegie Mellon University), Tze-Meng Low (Carnegie Mellon University), Nikolaos Alachiotis (Carnegie Mellon University), Berkin Akin (Carnegie Mellon University), Larry Pileggi (Carnegie Mellon University), James C. Hoe (Carnegie Mellon University), Franz Franchetti (Carnegie Mellon University) Microarchitectural Implications of Event-driven Server-side Web Applications Yuhao Zhu (UT Austin), Daniel Richins (UT Austin), Matthew Halpern (UT Austin), Vijay Janapa Reddi (UT Austin)
12:00pm \| 12:15pm	Conference Closing Room: Tapa Ballroom 2