| Sunday, November 30th | |
| 7:00-10:00 PM | Welcoming Reception (Empire room) |
| Monday, December 1st | |
| 8:00-8:30 | Welcome |
| 8:30-9:30 | Keynote Speech - Bob Colwell, Intel |
| 9:30-10:00 | Break |
| 10:00-12:00 | Session 1: Instruction Fetch (chair: Brad Calder, UCSD) |
| The Bi-Mode Branch Predictor, C. Lee (University of Michigan), I. Chen (University of Michigan), T. Mudge (University of Michigan) | |
| Path-Based Next Trace Prediction, Q. Jacobson (University of Wisconsin), E. Rotenberg (University of Wisconsin), J. Smith (University of Wisconsin) | |
| Improving Trace Cache Performance by Boosting the Effective Fetch Rate, D. Friendly (University of Michigan), S. Patel (University of Michigan), Y. Patt (University of Michigan) | |
| Reducing the Performance Impact of ICache Misses by Writing Instructions into the Reservation Stations Out-of-Order, J. Stark (University of Michigan), P. Racunas (University of Michigan), Y. Patt (University of Michigan) | |
| 12:00-1:00 | Lunch (provided) |
| 1:00-3:00 | Session 2: Data cache improvements (chair: Jim Bondi, TI) |
| On High-Bandwidth Data Cache Design for Multi-Issue Processors, J. Rivers (University of Michigan), G. Tyson (University of Michigan), T. Austin (Intel MRL), E. Davidson (University of Michigan) | |
| Run-time Spatial Locality Detection and Optimization, T. Johnson (University of Illinois), M. Merten (University of Illinois), W. Hwu (University of Illinois) | |
| A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine, G. Jones (Edinburgh University), N. Topham (Edinburgh University) | |
| The Design and Performance of a Conflict-avoiding Cache, N. Topham (Edinburgh University), A. Gonzalez (UPC, Barcelona), J. Gonzalez (UPC, Barcelona) | |
| Prediction Caches for Superscalar Processors, J. Bennett (Stanford University), M. Flynn (Stanford University) | |
| 3:00-3:30 | Break |
| 3:30-5:30 | Session 3: ILP Compiler Techniques I (chair: Jim Dehnert, SGI) |
| A Framework for Balancing Control Flow and Predication, D. August (University of Illinois), S. Mahlke (Hewlett Packard Labs), W. Hwu (University of Illinois) | |
| Evaluation of Scheduling Techniques on a SPARC-Based VLIW Testbed, S. Park (Seoul National University), S. Shim (Seoul National University), S. Moon (Seoul National University) | |
| Tuning Compiler Optimizations for Simultaneous Multithreading, J. Lo (University of Washington), S. Parekh (University of Washington), S. Eggers (University of Washington), H. Levy (University of Washington), D. Tullsen (University of California- San Diego) | |
| Exploiting Dead Value Information, M. Martin (University of Wisconsin), A. Roth (University of Wisconsin), C. Fischer (University of Wisconsin) | |
| 8:00-10:00 | SIGMICRO/TC-MICRO Business Meeting |
| Tuesday, December 2nd | |
| 8:00-10:00 AM | Session 4: Novel Microarchitectures (chair: Ilan Spillinger, Intel) |
| Trace Processors, E. Rotenberg (University of Wisconsin), Q. Jacobson (University of Wisconsin), Y. Sazeides (University of Wisconsin), J. Smith (University of Wisconsin) | |
| The Multicluster Architecture: Reducing Cycle Time Through Partitioning , K. Farkas (DEC-WRL), P. Chow (University of Toronto), N. Jouppi (DEC-WRL), Z. Vranesic (University of Toronto) | |
| Out-of-Order Vector Architectures, R. Espasa (UPC, Barcelona), M. Valero (UPC, Barcelona), J. Smith (University of Wisconsin) | |
| Initial Results on the Performance and Cost of Vector Microprocessors, C. Lee (University of Toronto), D. DeVries (University of Toronto) | |
| 10:00-10:30 | Break |
| 10:30-12:00 | Session 5: Memory for Embedded Processors (chair: Andy Wolfe, S3) |
| The Filter Cache: An Energy Efficient Memory Structure, J. Kin (University of California- Los Angeles), M. Gupta (University of California- Los Angeles), W. Mangione-Smith (University of California- Los Angeles) | |
| Improving Code Density Using Compression Techniques, C. Lefurgy (University of Michigan), P. Bird (University of Michigan), I. Chen (University of Michigan), T. Mudge (University of Michigan) | |
| Procedure Based Program Compression, D. Kirovski (University of California- Los Angeles), J. Kin (University of California- Los Angeles), W. Mangione-Smith (University of California- Los Angeles) | |
| 12:00-1:30 | Lunch |
| Some Reflections on Comptuer Engineering: 30 Years After the 360 Model 91 | |
| Speaker: Mike Flynn, Stanford | |
| 1:30-3:00 | Session 6: Load/Store Tuning (chair: Dean Tullsen, UCSD) |
| Improving the Accuracy and Performance of Memory Communication Through Renaming, G. Tyson (University of Michigan), T. Austin (Intel) | |
| Microarchitecture Support for Improving the Performance of Load Target Prediction, C. Chen (National Yunlin Institute of Technology), A. Wu (National. Yunlin Institute of Technology) | |
| Streamlining Inter-operation Memory Communication via Data Dependence Prediction, A. Moshovos (University of Wisconsin), G. Sohi (University of Wisconsin) | |
| 3:00-3:30 | Break |
| 3:30-5:30 | Session 7: Value Prediction (chair: Nancy Warter-Perez, CalSt-LA) |
| The Predictability of Data Values, Y. Sazeides (University of Wisconsin), J. Smith (University of Wisconsin) | |
| Value Profiling, B. Calder (University of California- San Diego), P. Feller (University of California- San Diego), A. Eustace (DEC-WRL) | |
| Can Program Profiling Support Value Prediction?, F. Gabbay (Technion - Israel Institute of Technology), A. Mendelson (Technion - Israel Institute of Technology) | |
| Highly Accurate Data Value Prediction using Hybrid Predictors, K. Wang (Clemson University), M. Franklin (Clemson University) | |
| 7:00-11:00 | Outing to ArtSpace in Raleigh's CityMarket, sponsored by Intel |
| Wednesday, December 3 | |
| 8:00-10:00 | Session 8: Profiling and Benchmarking (chair: Steve Beaty, MSCD) |
| ProfileMe: Hardware Support for Inst.-Level Profiling on Out-of-Order Processors, J. Dean (DEC-WRL), J. Hicks (DEC-CRL), Waldspurger (DEC-SRC), Weihl (DEC-SRC), Chrysos (DEC) | |
| Procedure Placement using Temporal Ordering Information, N. Gloy (Harvard University), T. Blackwell (Harvard University), M. Smith (Harvard University), B. Calder (University of California- San Diego) | |
| Predicting Data Cache Misses in Non-Numeric Applications Through Correlation Profiling, T. Mowry (Carnegie Mellon University), C. Luk (University of Toronto) | |
| Available Parallelism in Video Applications, H. Liao (Princeton University), A. Wolfe (Princeton University) | |
| MediaBench: A Tool for Evaluating Multimedia and Communications Systems, C. Lee (University of California- Los Angeles), M. Potkonjak (University of California- Los Angeles), W. Mangione-Smith (University of California- Los Angeles) | |
| 10:00-10:30 | Break |
| 10:30-12:00 | Session 9: ILP Compiler Techniques II (chair: Scott Mahlke, HP Labs) |
| Cache Sensitive Modulo Scheduling, F. Sanchez (UPC, Barcelona), A. Gonzalez (UPC, Barcelona) | |
| Unroll-and-Jam Using Uniformly Generated Sets, S. Carr (Michigan Technological University), Y. Guan (Shafi, Inc.) | |
| Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization, R. Gupta (University of Pittsburgh), D. Berson (Intel), J. Fang (Intel) |