Conference Program

Sunday, December 10, 2000

Workshops: 8:00am - 6:00pm

  • Feedback-Directed and Dynamic Optimization
    Chairs: Susan Eggers (Univeristy of Washington) Michael Smith (Harvard Univeristy)
  • Media Processors and DSPs
    Chairs: Bill Mangione-Smith (UCLA) David Baker (BOPS)
  • Multithreaded Execution, Architecture and Compilation
    Chairs: Walid Najjar (Colorado State University) Antonio Gonzalez (UPC Barcelona)
  • Kool Chips
    Chairs: Dirk Grunwald (University of Colorado) Mary Jane Irwin (Penn. State University) Trevor Mudge (University of Michigan)

  • Monday, December 11, 2000

    Welcome & First Keynote:
    8:00-9:30am, Monday December 11, Darrell Boggs (Intel)
    "Breathing Life Into a Paper Tiger"

    Session 1: Memory Hierarchy I
    10:00am-12:00pm, Monday December 11
    Session Chair: Ronny Ronen - Intel

    Eager Writeback - a Technique for Improving Bandwidth Utilization WINNER: Best Paper!
    (Presentation Slides)
    H.-H. Lee, G. S. Tyson (University of Michigan), M. Farrens (University of California, Davis)

    Silent Stores for Free
    (Presentation Slides)
    K. M. Lepak, M. H. Lipasti (University of Wisconsin - Madison)

    A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality
    (Presentation Slides)
    Z. Zhang, Z. Zhu, X. Zhang (College of William and Mary)

    Predictor-Directed Stream Buffers
    (Presentation Slides)
    T. Sherwood, S. Sair, B. Calder (University of California, San Diego)

    Lunch & Second Keynote:
    12:00-1:30 Monday December 11, Phil Kuekes (Hewlett-Packard)
    "Defect Tolerant Molecular Electronics: Algorithms, Architectures, and Atoms"

    Session 2: Superscalar Architecture
    1:30-3:30pm, Monday December 11
    Session Chair: Gary Tyson - University of Michigan

    On Pipelining Dynamic Instruction Scheduling Logic
    (Presentation Slides)
    J. Stark (Intel), M. D. Brown, Y. N. Patt (University of Texas at Austin)

    The Impact of Delay on the Design of Branch Predictors
    (Presentation Slides)
    D. A. Jimenez, S. W. Keckler, C. Lin (University of Texas at Austin)

    Improving BTB Performance in the Presence of DLLs
    (Presentation Slides)
    S. A. Vlaovic, E. S. Davidson, G. S. Tyson (University of Michigan)

    Efficient Checker Processor Design
    (Presentation Slides)
    S. Chatterjee, C. Weaver, T. Austin (University of Michigan)

    Session 3: Compilation
    4:00-5:30, Monday December 11
    Session Chair: Carol Thompson - Hewlett-Packard

    An Integrated Approach to Accelerate Data and Predicate Computations in Hyperblocks
    (Presentation Slides)
    A. Eichenberger (North Carolina State University), W. Meleis, S. Maradani (Northeastern University)

    Accurate and Efficient Predicate Analysis with Binary Decision Diagrams
    (Presentation Slides)
    J. W. Sias, W. W. Hwu (University of Illinois at Urbana-Champaign), D. I. August (Princeton University)

    Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture
    (Presentation Slides)
    J. Sanchez, A. Gonzalez (Universitat Politecnica de Catalunya)

    Tuesday, December 12, 2000

    Third Keynote:
    8:30-9:30am, Tuesday December 12, David Baker (BOPS)
    "A Whole New Ballgame - Supercomputing on Two AA Batteries"

    Session 4: Accelerator Architecture
    10:00am-12:00pm, Tuesday December 12
    Session Chair: Tom Conte - North Carolina State University

    Two-level Hierarchical Register File Organization for VLIW Processors
    (Presentation Slides)
    J. Zalamea, J. Llosa, E. Ayguade, M. Valero (Universitat Politecnica de Catalunya)

    PipeRench Implementation of the Instruction Path Coprocessor
    (Presentation Slides)
    Y. Chou, P. Pillai, H. Schmit, J. P. Shen (Carnegie Mellon University)

    Efficient Conditional Operations for Data-Parallel Architectures
    (Presentation Slides)
    U. J. Kapasi, W. J. Dally, S. Rixner, P. R. Mattson, J. D. Owens, B. Khailany (Stanford University)

    Flexible Hardware Acceleration for Multimedia Oriented Microprocessors
    (Presentation Slides)
    F. Vermeulen, F. Catthoor, L. Nachtergaele, D. Verkest, H. De Man (IMEC, Leuven)

    12:00-1:30pm Tuesday December 12

    Session 5: Low-Power Design
    1:30-3:30pm, Tuesday December 12
    Session Chair: Rajiv Gupta - University of Arizona

    Very Low Power Pipelines using Significance Compression
    (Presentation Slides)
    R. Canal, A. Gonzalez, J. E. Smith (University of Wisconsin - Madison)

    A Static Power Model for Architects
    (Presentation Slides) WINNER: Best Student Presentation!
    J. A. Butts, G. Sohi (University of Wisconsin - Madison)

    A Framework for Dynamic Energy-Efficiency and Temperature Management
    (Presentation Slides)
    W. Huang, J. Renau, S.-M. Yoo, J. Torrellas (University of Illinois at Urbana-Champaign)

    Dynamic Zero Compression for Cache Energy Reduction
    (Presentation Slides)
    L. Villa, M. Zhang, K. Asanovic (MIT)

    Session 6: Memory Hierarchy II
    4:00-6:00pm, Tuesday December 12
    Session Chair: Scott Mahlke - Hewlett-Packard

    Register Integration: A Simple and Efficient Implementation of Squash Re-Use
    (Presentation Slides)
    A. Roth, G. S. Sohi (University of Wisconsin - Madison)

    The Store-Load Address Table and Speculative Register Promotion
    (Presentation Slides)
    M. A. Postiff, D. A. Greene, T. N. Mudge (University of Michigan)

    Memory Hierarchy Reconfiguration For Energy And Performance In General-Purpose Processor Architectures
    (Presentation Slides)
    R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas (University of Rochester)

    Frequent Value Compression in Data Caches
    (Presentation Slides)
    J. Yang, Y. Zhang, R. Gupta (University of Arizona)

    Wednesday, December 13, 2000

    Session 7: Dynamic Translation and Multithreading
    8:00-10:00am, Wednesday December 13
    Session Chair: Kemal Ebcioglu - IBM

    A Study of Slipstream Processors
    (Presentation Slides)
    Z. Purser, K. Sundaramoorthy, E. Rotenberg (North Carolina State University)

    Relational Profiling: Enabling Thread Level Parallelism in Virtual Machines
    (Presentation Slides)
    T. H. Heil, J. E. Smith (University of Wisconsin - Madison)

    Calpa: A Tool for Automating Selective Dynamic Compilation
    (Presentation Slides)
    M. U. Mock, C. Chambers, S. J. Eggers (University of Washington)

    Increasing the Size of Atomic Instruction Blocks by using Control Flow Assertions
    (Presentation Slides)
    S. J. Patel, T. Tung, S. Bose, M. Crum (University of Illinois at Urbana-Champaign)

    Session 8: Superscalar Architecture II
    10:30-12:30pm, Wednesday December 13
    Session Chair: Bob Colwell - Intel

    Reducing Wire Delay Penalty through Value Prediction
    (Presentation Slides)
    J.-M. Parcerisa, A. Gonzalez (Universitat Politecnica de Catalunya)

    Compiler Controlled Value Prediction using Branch Predictor Based Confidence
    (Presentation Slides)
    E. Larson, T. Austin (University of Michigan)

    Instruction Distribution Heuristics for Quad-Clustered, Dynamically-Scheduled, Superscalar Processors
    (Presentation Slides)
    A. Baniasadi (Northwestern University), A. Moshovos (University of Toronto)

    Performance Improvement with Circuit-Level Speculation
    (Presentation Slides)
    T. Liu, S.-L. Lu (Intel)

    Closing and Awards:
    12:30-1:00pm, Wednesday December 13

    Tutorial: Dynamic Binary Translation and Optimization

    2:30-6:00pm, Wednesday December 13
    Erik Altman and Kemal Ebcioglu - IBM