Exploiting Data-Width Locality to Increase Superscalar Execution Bandwidth
Authors:
Gabriel H. Loh
Yale University
Department of Computer Science
Abstract:
In a 64-bit processor, many of the data values actually used in
computations require much narrower data-widths. In this study, we
demonstrate that instruction data-widths exhibit very strong temporal
locality and describe mechanisms to accurately predict data-widths.
To exploit the predictability of data-widths, we propose a
Multi-Bit-Width (MBW) microarchitecture which, when the opportunity
arises, takes the wires normally used to route the operands and bypass
the result of a 64-bit instruction, and instead uses them for multiple
narrow-width instructions. This technique increases the effective issue
width without adding many additional wires by reusing already existing
datapaths.
Compared to a traditional four-wide superscalar processor, our best MBW
configuration with a peak issue rate of eight IPC achieves a 7.1%
speedup on the simulated SPECint2000 benchmarks, which performs very
well when compared to a 7.9% speedup attainable by a processor with a
perfect data-width predictor.
Web Site:
Currently none. Alternate web source: http://www.cs.yale.edu/~loh