Generating Physical Addresses Directly for Saving Instruction TLB Energy
Authors:
Abstract:
Power consumption and power density for the Transla-tion
Lookaside Buffer (TLB) are important considerations
not only in its design, but can have a consequence on cache
design as well. This paper embarks on a new philosophy
for reducing the number of accesses to the instruction TLB
(iTLB) for power and performance optimizations. The over-all
idea is to keep a translation currently being used in
a register and avoid going to the iTLB as far as possible
- until there is a page change. We propose four different
approaches for achieving this, and experimentally demon-strate
that one of these schemes that uses a combination of
compiler and hardware enhancements can reduce iTLB dy-namic
power by over 85% in most cases.
These mechanisms can work with different instruction-cache
(iL1) lookup mechanisms and achieve significant
iTLB power savings without compromising on performance.
Their importance grows with higher iL1 miss rates and
larger page sizes. They can work very well with large iTLB
structures, that can possibly consume more power and take
longer to lookup, without the iTLB getting into the com-mon
case. Further, we also experimentally demonstrate that
they can provide performance savings for virtually-indexed,
virtually-tagged iL1 caches, and can even make physically-indexed,
physically-tagged iL1 caches a possible choice for
implementation.