Compiling for Instruction Cache Performance on a Multithreaded Architecture
Authors:
Rakesh Kumar, UCSD
Dean M. Tullsen, UCSD
Abstract:
Instruction cache aware compilation seeks to lay out a program in memory
in such a way that cache conflicts between procedures are
minimized. It does this through profile-driven knowledge of
procedure invocation patterns. On a multithreaded architecture,
however, more conflicts may arise between threads
than between procedures on the same thread. This research examines
opportunities for the compiler to optimize instruction cache layout
on a multithreaded architecture. We examine scenarios where (1) the
compiler has knowledge about multiple programs that will be or are
likely to be co-scheduled, and where (2) the compiler has no knowledge
at compile time of which applications will be co-scheduled. We present
solutions for both environments.
Web Site:
http://www-cse.ucsd.edu/users/tullsen/research.html