Optimizing Pipelines for Power and Performance
Authors:
Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose,
Victor Zyuban, Philip N. Strenski, Philip G. Emma
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598
Abstract:
During the concept phase and definition of next generation high-end
processors, power and performance will need to be weighted appropriately to
deliver competitive cost/performance. It is not enough to adopt a
CPI-centric view alone in early-stage definition studies. One of the
fundamental issues confronting the architect at this stage is the choice
of pipeline depth and target frequency. In this paper
we present an optimization methodology that starts with an analytical
power-performance model to derive optimal pipeline depth for a
superscalar processor. The results are validated and further
refined using detailed simulation based analysis. As part of the
power-modeling methodology, we have developed equations that model the
variation of energy as a function of pipeline depth. Our results using
a set of SPEC2000 applications show that when both power and performance
are considered for optimization, the optimal clock period is around 18
FO4. We also provide a detailed sensitivity analysis of the optimal
pipeline depth against key assumptions of these energy models.