Pointer Cache Assisted Prefetching
Authors:
Jamison Collins, Suleyman Sair, Brad Calder, and Dean Tullsen
(University of California, San Diego)
Abstract:
Data prefetching effectively reduces the negative effects of long load
latencies on the performance of modern processors. Hardware
prefetchers employ hardware structures to predict future memory
addresses based on previous patterns. Thread-based prefetchers use
portions of the actual program code to determine future load addresses
for prefetching.
This paper proposes the use of a pointer cache, which tracks pointer
transitions, to aid prefetching. The pointer cache provides, for a
given pointer's effective address, the base address of the object
pointed to by the pointer. We examine using the pointer cache in a
wide issue superscalar processor as a value predictor and to aid
prefetching when a chain of pointers is being traversed. When a load
misses in the L1 cache, but hits in the pointer cache, the first two
cache blocks of the pointed to object are prefetched. In addition, the
load's dependencies are broken by using the pointer cache hit as a
value prediction.
We also examine using the pointer cache to allow speculative
precomputation to run farther ahead of the main thread of execution
than in prior studies. Previously proposed thread-based prefetchers
are limited in how far they can run ahead of the main thread when
traversing a chain of recurrent dependent loads. When combined with
the pointer cache, a speculative thread can make better progress ahead
of the main thread, rapidly traversing data structures in the face of
cache misses caused by pointer transitions.
Web Site:
http://www.cs.ucsd.edu/~calder/abstracts/MICRO-02-PCache.html