Thermal-Management Issues for Microprocessors

A tutorial held in conjunction with MICRO-35

Istanbul, Turkey

This three-hour tutorial focuses on how heat is generated and dissipated in modern microprocessors. Many analysts suggest that increasing power density and resulting difficulties in managing on-chip temperatures are some of the most urgent obstacles to continued scaling of VLSI systems within the next five to ten years. Just as has been done before for power-aware computing, "temperature-aware" computing must be approached not just from the packaging and circuit-design communities, but also from the processor-architecture community. In particular the solutions developed by the VLSI and architecture communities are often synergistic and typically require cooperation. Circuit techniques can reduce heat dissipation for all circuits of a particular style, while processor-architecture solutions can often use global, runtime knowledge to change the behavior of large portions of the processor (typically with the support of appropriate circuit techniques). There is growing interest in architecture-level solutions, as evidenced by recent work on fetch throttling and dynamic voltage scaling in response to thermal stress.

The biggest obstacles today in pursing thermal-management solutions at the architecture level are the lack of accurate modeling tools and the lack of general knowledge in the architecture community about heat-related issues. Yet the accuracy of thermal modeling has a substantial effect on the accuracy of thermal-management studies and the conclusions they draw. Architecture researchers are therefore limited to crude and inaccurate estimation techniques and are unable to effectively develop and evaluate techniques for thermal management.

This tutorial is primarily intended for an audience of architecture researchers who are already moderately acquainted with issues in modeling and designing power-aware microarchitectures, but who may have little or no familiarity with issues related to heat dissipation. We also welcome the participation of those more experienced in these issues.

The tutorial will explain the way heat is dissipated at different levels of the overall microprocessor package, describe simple modeling techniques, carefully examine the variety of issues related to on-chip temperature sensing (including power delivery and dI/dt issues), and review recently proposed techniques for thermal management.

Tutorial Organizers:

Kevin Skadron (Virgina)[email protected]
Mircea Stan (Virgina) [email protected]
David Brooks, Harvard [email protected]
 

Bios:


Kevin Skadron is an Assistant Professor of Computer Science at the University of Virginia (http://www.cs.virginia.edu/~skadron). He received his PhD in Computer Science from Princeton University, and bachelors' degrees in Electrical and Computer Engineering and also Economics from Rice University. At U.Va., he directs the Laboratory for Computer Architecture at Virginia (LAVA). In addition to power and thermal issues, the LAVA group is also pursuing research in branch prediction and techniques for fast and accurate microprocessor simulation. Skadron has been on the program committees for several conferences, is general co-chair of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT), and helped to launch Computer Architecture Letters, a new short-format, refereed journal being produced by the IEEE Computer Society TCCA.

Mircea Stan is an Associate Professor of Electrical and Computer Engineering at the University of Virginia. He received the Ph.D. and M.S. degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst, and the Diploma in Electronics and Communications from "Politehnica" University in Bucharest, Romania. At U.Va., he directs the High-Performance Low-Power Laboratory (HPLP), pursing research in the areas of high-performance and low-power VLSI, mixed-mode analog and digital circuits, computer arithmetic, embedded systems, and nanoelectronics. He has more than eight years of industrial experience as an R&D Engineer in Bucharest, Tokyo and Atlanta, and has been a visiting faculty at IBM in 2000 and at Intel in 2002 and 1999. He has been on the technical committees for several conferences, has been an Associate Editor for the IEEE Transactions on VLSI Systems since 2001, and is a senior member of the IEEE.

David Brooks is an Assistant Professor of Computer Science at Harvard University. He received his PhD from Princeton University in 2001 and his BS degree from the University of Southern California, both in Electrical Engineering. After receiving his PhD, David spent 1 year working at IBM TJ Watson Research Center and previously spent summers at Intel Corporation. His research interests include power-efficient, high-performance computer architectures and technology trends in microprocessor design.