39th International Symposium on
Microarchitecture **** Click here for a detailed schedule with Times and Locations ***
Sunday, December 10, 2006
Monday, December 11, 2006
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design Fayez Mohamood, Georgia Institute of Technology Michael Healy, Georgia Institute of Technology Sung Kyu Lim, Georgia Institute of Technology Hsien-Hsin S. Lee, Georgia Institute of Technology Yield-Aware Cache Architectures Serkan Ozdemir, Northwestern University Debjit Sinha, Northwestern University Gokhan Memik, Northwestern University Jonathan Adams, Northwestern University Hai Zhou, Northwestern University Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware Smruti Sarangi, University of Illinois at Urbana-Champaign Abhishek Tiwari, University of Illinois at Urbana-Champaign Josep Torrellas, University of Illinois at Urbana-Champaign PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection Shan Lu, University of Illinois at Urbana-Champaign Pin Zhou, University of Illinois at Urbana-Champaign Wei Liu, University of Illinois at Urbana-Champaign Yuanyuan Zhou, University of Illinois at Urbana-Champaign Josep Torrellas, University of Illinois at Urbana-Champaign Noon-1:30pm: Lunch
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths Hyesoon Kim, University of Texas - Austin Jose A. Joao, University of Texas - Austin Onur Mutlu, Microsoft Research Yale N. Patt, University of Texas - Austin Head and Tail Duplication for Convergent Hyperblock Formation Bertrand A. Maher, University of Texas - Austin Aaron Smith, University of Texas - Austin Doug Burger, University of Texas - Austin Kathryn McKinley, University of Texas - Austin Data-Dependency Graph Transformations for Superblock Scheduling Mark Heffernan, University of California - Davis Kent Wilken, University of California - Davis Ghassan Shobaki, University of California - Davis Dataflow Predication Aaron Smith, University of Texas - Austin Doug Burger, University of Texas - Austin Steve Keckler, University of Texas - Austin Kathryn McKinley, University of Texas - Austin Ramdas Nagarajan, University of Texas - Austin Karu Sankaralingam, University of Texas - Austin Robert McDonald, University of Texas - Austin
Authentication Control Point and its Implications for Secure Processor Design Weidong Shi, Motorola Lab Hsien-Hsin S. Lee, Georgia Institute of Technology Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection Xiaotong Zhuang, Georgia Institute of Technology Tao Zhang, Georgia Institute of Technology Santosh Pande, Georgia Institute of Technology Memory Protection through Dynamic Access Control Kun Zhang, Georgia Institute of Technology Tao Zhang, Georgia Institute of Technology Santosh Pande, Georgia Institute of Technology LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting General Security Attacks Feng Qin, Ohio State University Zhenmin Li, University of Illinois at Urbana-Champaign Yuanyuan Zhou, University of Illinois at Urbana-Champaign Cheng Wang, Intel Research Lab Ho-seop Kim, Intel Research Lab Youfeng Wu, Intel Research Lab 3:30-4pm: Break
Fairness and Throughput in Switch on Event Multithreading Ron Gabor, Tel-Aviv University (TAU) Shlomo Weiss, Tel-Aviv University (TAU) Avi Mendelson, Intel A Predictive Performance Model for Superscalar Processors P. J. Joseph, Freescale Kapil Vaswani, Indian Institute of Science Matthew J. Thazhuthaveetil, Indian Institute of Science Serialization-Aware Mini-Graphs: Performance with Fewer Resources Anne Bracy, University of Pennsylvania and Intel Amir Roth, University of Pennsylvania
Architectural Support for Software Transactional Memory Bratin Saha, Intel Corporation Ali-Reza Adl-Tabatabai, Intel Corporation Quinn Jacobson, Intel Corporation Virtually Pipelined Network Memory Banit Agrawal, University of California - Santa Barbara Timothy Sherwood, University of California - Santa Barbara Fair Queuing CMP Memory Systems Kyle J. Nesbit, University of Wisconsin - Madison Nidhi Aggarwal, University of Wisconsin - Madison James Laudon, Sun Microsystems James E. Smith, University of Wisconsin - Madison 5:30-6pm: Break
Tuesday, December 12, 2006
9-9:30am: Break
Reunion: Complexity-Effective Multicore Redundancy Jared C. Smolens, Carnegie Mellon University Brian T. Gold, Carnegie Mellon University Babak Falsafi, Carnegie Mellon University James C. Hoe, Carnegie Mellon University Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers Jack Sampson, University of California - San Diego Ruben Gonzalez, UPC Barcelona Jean-Francois Collard, HP Labs Norman P. Jouppi, HP Labs Mike Schlansker, HP Labs Brad Calder, University of California - San Diego and Microsoft CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs Pierre Palatin, INRIA Yves Lhuillier, INRIA Olivier Temam, INRIA Support for High-Frequency Streaming in CMPs Ram Rangan, Princeton University Neil Vachharajani, Princeton University Adam Stoler, Princeton University Guilherme Ottoni, Princeton University David August, Princeton University George Cai, Intel Corporation 11:30am-1pm: Lunch
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All Samantika Subramaniam, Georgia Institute of Technology Gabriel H. Loh, Georgia Institute of Technology NoSQ: Store-Load Communication without a Store Queue Tingting Sha, University of Pennsylvania Milo M. K. Martin, University of Pennsylvania Amir Roth, University of Pennsylvania DMDC: Delayed Memory Dependence Checking through Age-based Filtering Fernando Castro, University Complutense of Madrid Daniel Chaver, University Complutense of Madrid Luis Pinuel, University Complutense of Madrid Manuel Prieto, University Complutense of Madrid Michael C. Huang, University of Rochester Francisco Tirado, University Complutense of Madrid
Coherence Ordering for Ring-based Chip Multiprocessors Michael R. Marty, University of Wisconsin - Madison Mark D. Hill, University of Wisconsin - Madison In-Network Cache Coherence Noel Eisley, Princeton University Li-Shiuan Peh, Princeton University Li Shang, Queens University ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers Chrysostomos A. Nicopoulos, Pennsylvania State University Dongkook Park, Pennsylvania State University Jongman Kim, Pennsylvania State University Narayanan Vijaykrishnan, Pennsylvania State University Mazin S. Yousif, Intel Corporation Chita R. Das, Pennsylvania State University 2:30-3pm: Break
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget Canturk Isci, Princeton University Alper Buyuktosunoglu, IBM Pradip Bose, IBM Margaret Martonosi, Princeton University Chen-Yong Cher, IBM Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units Ahmed Youssef, University of Waterloo Mohab Anis, University of Waterloo Mohamed Elmasry, University of Waterloo Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management Canturk Isci, Princeton University Gilberto Contreras, Princeton University Margaret Martonosi, Princeton University
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads Ranjith Subramanian, Georgia Institute of Technology Yannis Smaragdakis, Georgia Institute of Technology Gabriel H. Loh, Georgia Institute of Technology Memory Prefetching Using Adaptive Stream Detection Ibrahim Hur, University of Texas - Austin and IBM Calvin Lin, University of Texas - Austin Scalable Cache Miss Handling for High Memory-Level Parallelism James Tuck, University of Illinois at Urbana-Champaign Luis Ceze, University of Illinois at Urbana-Champaign Josep Torrellas, University of Illinois at Urbana-Champaign
Wednesday, December 13, 2006
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches Moinuddin K. Qureshi, University of Texas - Austin Yale N. Patt, University of Texas - Austin Molecular Caches: A Caching Structure for Dynamic Creation of Application-Specific Heterogeneous Cache Regions Keshavan Varadarajan, Indian Institute of Science, Bangalore S. K. Nandy, Indian Institute of Science, Bangalore Vishal Sharda, Indian Institute of Science, Bangalore Amrutur Bharadwaj, Indian Institute of Science, Bangalore Ravi Iyer, Intel Corporation Srihari Makineni, Intel Corporation Donald Newell, Intel Corporation ASR: Adaptive Selective Replication for CMP Caches Bradford M. Beckmann, University of Wisconsin - Madison Michael R. Marty, University of Wisconsin- Madison David A. Wood, University of Wisconsin- Madison Managing Distributed, Shared L2 Caches through OS-Level Page Allocation Sangyeun Cho, University of Pittsburgh Lei Jin, University of Pittsburgh 10-10:30am: Break
Die Stacking (3D) Microarchitecture Bryan Black, Intel Murali Annavaram, Intel Ned Brekelbaum, Intel John DeVale, Intel Lei Jiang, Intel Gabriel H. Loh, Georgia Institute of Technology Don McCauley, Intel Pat Morrow, Intel Donald W. Nelson, Intel Daniel Pantuso, Intel Paul Reed, Intel Jeff Rupley, Intel Sadasivan Shankar, Intel John Shen, Intel Clair Webb Intel Distributed Microarchitectural Protocols in the TRIPS Prototype Processor Karthikeyan Sankaralingam, University of Texas - Austin Ramadass Nagarajan, University of Texas - Austin Robert McDonald, University of Texas - Austin Rajagopalan Desikan, University of Texas - Austin and AMD Saurabh Drolia, University of Texas - Austin and Microsoft Madhu Saravana Sibi Govindan, University of Texas - Austin Paul Gratz, University of Texas - Austin Divya Gulati, University of Texas - Austin Heather Hanson, University of Texas - Austin Changkyu Kim, University of Texas - Austin Haiming Liu, University of Texas - Austin Nitya Ranganathan, University of Texas - Austin Simha Sethmadhavan, University of Texas - Austin Sadia Sharif, University of Texas - Austin Premkishore Shivakumar, University of Texas - Austin Stephen W. Keckler, University of Texas - Austin Doug Burger, University of Texas - Austin Leveraging Optical Technology in Future Bus-based Chip Multiprocessors Nevin Kirman, Cornell University Meyrem Kirman, Cornell University Rajeev K. Dokania, Cornell University Jose F. Martinez, Cornell University Alyssa B. Apsel, Cornell University Matthew A. Watkins, Cornell University David H. Albonesi, Cornell University Mitigating the Impact of Process Variations on CPU Register File and Execution Units Xiaoyao Liang, Harvard University David Brooks, Harvard University
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