Sunday, December 2, 2007

6:30pm: Reception dinner in the Promenade Ballroom.

Monday, December 3, 2007

All sessions are in the Grand Ballroom.

8:30-8:45am: Welcome

10:00-10:30am: Break

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 -- slides
Naveen Muralimanohar, University of Utah

Rajeev Balasubramonian, University of Utah

Norm Jouppi, HP Labs
 

Process Variation Tolerant 3T1D-Based Cache Architectures
Xiaoyao Liang, Harvard University

Ramon Canal, Universitat Politecnica de Catalunya

Gu-Yeon Wei, Harvard University

David Brooks, Harvard University

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing -- slides
Radu Teodorescu, University of Illinois at Urbana-Champaign

Jun Nakano, University of Illinois at Urbana-Champaign

Abhishek Tiwari, University of Illinois at Urbana-Champaign

Josep Torrellas, University of Illinois at Urbana-Champaign

Noon-1:30pm: Lunch

Optimal versus Heuristic Global Code Scheduling -- slides
Sebastian Winkel, Intel Corporation

Global Multi-Threaded Instruction Scheduling
Guilherme Ottoni, Princeton University

David August, Princeton University

Revisiting the Sequential Programming Model for Multi-Core -- slides
Matthew Bridges, Princeton University

Neil Vachharajani, Princeton University

Yun Zhang, Princeton University

Thomas Jablin, Princeton University

David August, Princeton University

Penelope: the NBTI-Aware Processor -- slides
Jaume Abella, Intel Barcelona Research Center, Intel Labs - UPC

Xavier Vera, Intel Barcelona Research Center, Intel Labs - UPC

Antonio González, Intel Barcelona Research Center, Intel Labs – UPC

Software-Based On­Line Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation -- slides
Kypros Constantinides, University of Michigan

Onur Mutlu, Microsoft Research

Todd Austin, University of Michigan

Valeria Bertacco, University of Michigan

Self-calibrating Online Wearout Detection -- slides
Jason Blome, University of Michigan

Shuguang Feng, University of Michigan

Shantanu Gupta, University of Michigan

Scott Mahlke, University of Michigan

3:00-3:30pm: Break

Implementing Signatures for Transactional Memory
Daniel Sanchez Martin, University of Wisconsin-Madison

Luke Yen, University of Wisconsin-Madison

Mark D. Hill, University of Wisconsin-Madison

Karthikeyan Sankaralingam, University of Wisconsin-Madison

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs -- slides
Mrinmoy Ghosh, Georgia Institute of Technology

Hsien-Hsin S. Lee, Georgia Institute of Technology

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors -- slides
Onur Mutlu, Microsoft Research

Thomas Moscibroda, Microsoft Research

Impact of Cache Coherence Protocols on the Processing of Network Traffic -- slides
Amit Kumar, Intel Corporation

Ram Huggahalli, Intel Corporation

Flattened Butterfly Topology for On-Chip Networks
John Kim, Stanford University

James Balfour, Stanford University

William Dally, Stanford University

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly -- slides
Brian Rogers, North Carolina State University

Siddhartha Chhabra, North Carolina State University

Milos Prvulovic, Georgia Institute of Technology

Yan Solihin, North Carolina State University

5:00-5:30pm: Break

5:30pm-6:30pm: Panel Session: Computing Beyond Von Neumann

Moderator:

Mark Hill, University of Wisconsin - Madison

Panelists:

Doug Burger, University of Texas - Austin

Wen-mei W. Hwu, University of Illinois - Urbana-Champaign

Mikko Lipasti, University of Wisconsin - Madison

Mark Oskin, University of Washington

Yale Patt, University of Texas - Austin

James Shapiro, University of Chicago

9:00-11:00pm: Business Meeting

Tuesday, December 4, 2007
All sessions are in the Grand Ballroom.

9:30-10:00am: Break

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Jangwoo Kim, Carnegie Mellon University

Nikos Hardavellas, Carnegie Mellon University

Ken Mai, Carnegie Mellon University

Babak Falsafi, Carnegie Mellon University

James Hoe, Carnegie Mellon University

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores -- slides
Albert Meixner, Duke University

Michael E. Bauer, Duke University

Daniel Sorin, Duke University

Leveraging 3D Technology for Improved Reliability
Niti Madan, University of Utah

Rajeev Balasubramonian, University of Utah

Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning
Francisco Mesa-Martinez, UCSC

Jose Renau, UCSC
 

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators -- slides
Derek Chiou, University of Texas at Austin

Dam Sunwoo, University of Texas at Austin

Nikhil Ajay Patil, University of Texas at Austin

Joonsoo Kim, University of Texas at Austin

Nikhil A. Patil, University of Texas at Austin

William Reinhart, University of Texas at Austin

Darrel Eric Johnson, University of Texas at Austin
Jebediah Keefe, University of Texas at Austin

Hari Angepat, University of Texas at Austin

Microarchitectural Design Space Exploration Using An Architecture-Centric Approach
Christophe Dubach, University of Edinburgh

Timothy Jones, University of Edinburgh

Michael O'Boyle, University of Edinburgh

Informed Microarchitecture Design Space Exploration using Workload Dynamics -- slides
Chang-burm Cho, University of Florida

Wangyuan Zhang, University of Florida

Tao Li, University of Florida

Time Interpolation: So Many Metrics, So Few Registers -- slides
Todd Mytkowicz, University of Colorado, Boulder

Peter F. Sweeney, IBM Research

Matthias Hauswirth, University of Lugano, CH

Amer Diwan, University of Colorado, Boulder

12noon-1:30pm: Lunch

Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications -- slides
Yuan Chou, Sun Microsystems

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy -- slides
Jason Zebchuk, University of Toronto

Elham Safi, University of Toronto

Andreas Moshovos, University of Toronto

Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors -- slides
Karin Strauss, University of Illinois at Urbana-Champaign

Xiaowei Shen, IBM Research

Josep Torrellas, University of Illinois at Urbana-Champaign

A Framework for Providing Quality of Service in Chip Multi-Processors -- slides
Fei Guo, North Carolina State University

Yan Solihin, North Carolina State University

Li Zhao, Intel Corporation

Ravi Iyer, Intel Corporation

A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs -- slides
William Thies, Massachusetts Institute of Technology

Vikram Chandrasekhar, Massachusetts Institute of Technology

Saman Amarasinghe, Massachusetts Institute of Technology

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
Michael Chu, University of Michigan

Rajiv Ravindran, Hewlett Packard

Scott Mahlke, University of Michigan

Wednesday, December 5, 2007
All sessions are in the Grand Ballroom.

Composable Lightweight Processors
Changkyu Kim, Intel Corporation

Simha Sethumadhavan, University of Texas at Austin

M.S. Govindan, University of Texas at Austin

Nitya Ranganathan, University of Texas at Austin

Divya Gulati, University of Texas at Austin

Doug Burger, University of Texas at Austin

Stephen W. Keckler, University of Texas at Austin

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration
Thomas Yeh, UCLA

Petros Faloutsos, UCLA

Milos Ercegovac, UCLA

Sanjay Patel, University of Illinois at Urbana-Champaign

Glenn Reinman, UCLA

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow -- slides
Wilson W. L. Fung, University of British Columbia

Ivan Sham, University of British Columbia

George Yuan, University of British Columbia

Tor M. Aamodt, University of British Columbia

10-10:30am: Break

Scavenger: A New Last Level Cache Architecture with Global Block Priority -- slides
Arkaprava Basu, Indian Institute of Technology, Kanpur

Nevin Kirman, Cornell University

Meyrem Kirman, Cornell University

Mainak Chaudhuri, Indian Institute of Technology, Kanpur

Jose Martinez, Cornell University

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache -- slides
Stephen Hines, Florida State University

David Whalley, Florida State University

Gary Tyson, Florida State University

Emulating Optimal Replacement with a Shepherd Cache -- slides
Kaushik Rajan, Indian Institute of Science

Govindarajan Ramaswamy, Indian Institute of Science