Sunday, 8:30 AM – 5:00 PM: Registration

Location: Hilton lobby level

Sunday, 6:00 PM – 8:00 PM: Conference Reception

Location: George Bellows Ballroom (Hilton, lower level)

Monday, October 14

7:30 AM – 5:00 PM: Registration

Location: Union Station Foyer (North Building, 1st Floor)

7:30 AM – 8:15 AM: Breakfast

Location: Union Station Foyer & Union Station C (North Building, 1st Floor)

8:15 AM – 8:30 AM: Opening Remarks

Location: Union Station B (North Building, 1st Floor)

8:30 AM – 9:30 AM: Keynote by Krste Asanovic

Unlike the historic microprocessor era, where computers were built with standard silicon parts, most computation is now performed by SoCs, where every new SoC design is an opportunity for application-specific customization. But realizing the potential benefits of greater specialization in commercial products requires advances in design productivity, as unsustainable SoC hardware and software design cost scaling is already a far greater challenge than transistor scaling. This productivity challenge lies behind the resurgence of interest in open-source hardware. The hope is that the hardware industry can replicate the success of the software industry, where innovative products are often created by mostly reusing existing code from open-source software stacks. While the open-source hardware movement has recently been driven by the widespread momentum behind RISC-V, a free and open ISA is only one component among many that will be needed to create a vibrant open SoC ecosystem. The architecture community is ideally placed to help fill out the open-source SoC stack and enable a new era of frictionless open-source hardware innovation.

Krste Asanovic is a Professor in the EECS Department at the University of California, Berkeley. He is also Chairman of the Board of the RISC-V Foundation, and is a co-founder and Chief Architect at SiFive. His main research areas are computer architecture, VLSI design, parallel programming, and operating system design, and he is co-director of the Berkeley ADEPT lab, which is aiming to reignite hardware innovation by reducing the cost and effort of deploying custom silicon for new cloud and edge applications. He is an ACM Fellow and an IEEE Fellow.

9:30 AM – 10:30 AM: Lightning Talks I

Location: Union Station B (North Building, 1st Floor)
Session Chair: Aasheesh Kohli

10:30 AM – 11:00 AM: Coffee Break

Location: Union Station Foyer (North Building, 1st Floor)

11:00 AM – 12:00 PM

Session Chair: Tushar Krishna
Wire-Aware Architecture and Dataflow for CNN Accelerators
Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon (University of Utah)

ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning
Alberto Delmüs, Sayeh Sharify, Isak Edo (University of Toronto); Dylan Malone Stuart (Toronto); Omar Mohamed Awad (University of Toronto); Patrick Judd (NVIDIA); Mostafa Mahmoud, Milos Nikolic, Kevin Siu (Toronto); Zissis Poulos and Andreas Moshovos (University of Toronto)

Best Paper Winner
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney (NVIDIA); Priyanka Raina (Stanford University); Stephen G Tell and Yanqing Zhang (NVIDIA); William J. Dally (NVIDIA/Stanford); Joel Emer (NVIDIA, MIT); C. Thomas Gray and Brucek Khailany (NVIDIA); Stephen W. Keckler (NVIDIA and UT-Austin)
Session Chair: Chris Fletcher
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Thomas Bourgeat and Ilia Lebedev (MIT); Andy Wright and Sizhuo Zhang (Massachusetts Institute of Technology); Arvind Arvind (MIT); Srinivas Devadas (Massachusetts Institute of Technology)

Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference
Austin Harris, Shijia Wei, Prateek Sahu, Pranav Kumar, Mohit Tiwari (The University of Texas at Austin); Todd Austin (University of Michigan)

CleanupSpec: An "Undo" Approach to Safe Speculation
Gururaj Saileshwar and Moinuddin Qureshi (Georgia Institute of Technology)
Session Chair: Yoav Etsion
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing
Elaheh Sadredini, Reza Rahimi, Vaibhav Verma, Mircea Stan, Kevin Skadron (University of Virginia)

ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs
Fei Gao, Georgios Tziantzioulis, David Wentzlaff (Princeton University)

CASCADE: Connecting RRAMs to Extend Analog Dataflow in an End-to-End In-Memory Processing Paradigm
Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang (University of Michigan)

12:00 PM – 1:30 PM: Lunch

Location: George Bellows Ballroom (Hilton, lower level)

1:30 PM – 3:10 PM

Session Chair: Minsoo Rhu
ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions
Berkin Akin (Google); Zeshan A. Chishti and Alaa R. Alameldeen (Intel)

Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating
Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, Edward Suh (Cornell University)

SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks
Ashish Gondimalla (Purdue); Noah Chesnut (unaffiliated); Mithuna Thottethodi (Purdue); T. N. Vijaykumar (Purdue University)

EDEN: Enabling Approximate DRAM for DNN Inference using Error-Resilient Neural Networks
Skanda Koppula, Konstantinos Kanellopoulos, Taha Shahroodi, Roknoddin Azizi, Giray Yaglikci, Lois Orosa (ETH Zurich); Onur Mutlu (ETH Zurich, CMU)

eCNN: a Block-Based and Highly-Parallel CNN Accelerator for Edge Inference
Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen (National Tsing Hua University) Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen (National Tsing Hua University)
Session Chair: Heiner Litz
Best Paper Runner-Up
Dynamic Multi-Resolution Data Storage
Yu-Ching Hu (University of California, Riverside); Murtuza Taher Lokhandwala (North Carolina State University); Te I (Google); Hung-Wei Tseng (University of California, Riverside)

Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs
Youngseop Shim, Myungsuk Kim, Myoungjun Chun, Jisung Park, Yoona Kim, Jihong Kim (Seoul National University)

DeepStore: In-Storage Acceleration for Intelligent Queries
Vikram Sharma Mailthody, Zaid Qureshi, Weixin Liang, Ziyan Feng, Simon Garcia de Gonzalo, Youjie Li (University of Illinois, Urbana-Champaign); Hubertus Franke and Jinjun Xiong (IBM Research); Jian Huang and Wen-mei Hwu (University of Illinois, Urbana-Champaign)

FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling
Mohammadamin Ajdari (POSTECH); Wonsik Lee, Pyeongsu Park, Joonsung Kim, Jangwoo Kim (Seoul National University)
Session Chair: Xuehai Qian
Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes
Swamit Tannu and Moinuddin Qureshi (Georgia Institute of Technology)

Partial Compilation of Variational Algorithms for Noisy Intermediate-Scale Quantum Machines
Pranav Gokhale, Yongshan Ding, Thomas Propson, Christopher Winkler, Nelson Leung, Yunong Shi, David I. Schuster, Henry Hoffmann, Frederic T. Chong (University of Chicago)

Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias
Swamit Tannu and Moinuddin Qureshi (Georgia Institute of Technology)

A Case for Multi-Programming Quantum Computers
Poulami Das (Georgia Tech); Swamit Tannu (Georgia Institute of Technology); Prashant J. Nair (The University of British Columbia); Moinuddin Qureshi (Georgia Tech)

3:10 PM – 4:30 PM: Poster Session I, SRC Poster Session, & Coffee

Location: Union Station Foyer (North Building, 1st Floor)

4:30 PM – 5:50 PM

Session Chair: Jian Huang
FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning
Eunjin Baek, Hunjun Lee (Seoul National University); Youngsok Kim (Yonsei University); Jangwoo Kim (Seoul National University)

ExTensor: An Accelerator for Sparse Tensor Algebra
Kartik Hegde and Hadi Asghari-Moghaddam (University of Illinois at Urbana-Champaign); Michael Pellauer, Neal Crago, Aamer Jaleel (Nvidia); Edgar Solomonik (University of Illinois at Urbana-Champaign); Joel Emer (Nvidia/MIT); Christopher Fletcher (University of Illinois at Urbana-Champaign)

GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment
Anirban Nag, C.N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon (University of Utah)

Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-Way Merge Parallelization
Fazle Sadi, Joe Sweeney, Tze Meng Low, James C. Hoe, Larry Pileggi, Franz Franchetti (Carnegie Mellon University)
Session Chair: Brad Beckmann
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs
Maohua Zhu (University of California, Santa Barbara); Tao Zhang and Zhenyu Gu (Alibaba Inc.); Yuan Xie (Univ. of California Santa Barbara)

NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs
Oreste Villa, Mark Stephenson, David Nellans (NVIDIA); Stephen W. Keckler (NVIDIA and UT-Austin)

Tangram: Integrated Control of Heterogeneous Computers
Raghavendra Pradyumna Pothukuchi (University of Illinois at Urbana-Champaign); Joseph L. Greathouse, Karthik Rao, Christopher Erb, Leonardo Piga (Advanced Micro Devices, Inc.); Petros Voulgaris and Josep Torrellas (University of Illinois at Urbana-Champaign)

CoSpec: Compiler Directed Speculative Intermittent Computation
Jongouk Choi (Purdue); Qingrui Liu (Xilinx); Changhee Jung (Purdue)
Session Chair: Nathan Beckmann
Applying Deep Learning to the Cache Replacement Problem
Zhan Shi, Xiangru Huang, Akanksha Jain, Calvin Lin (University of Texas at Austin)

DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management
Ziqiang Huang (University of Waterloo); Jose A. Joao and Alejandro Rico (Arm Research); Andrew D. Hilton and Benjamin C. Lee (Duke University)

Leveraging Caches to Accelerate Associative Containers
Guowei Zhang and Daniel Sanchez (MIT)

Touche: Towards Ideal and Efficient Cache Compression by Mitigating Tag Area Overheads
Seokin Hong (Kyungpook National University); Alper Buyuktosunoglu, Michael Healy, Bulent Abali (IBM Research); Prashant J. Nair (The University of British Columbia)

6 PM – 8 PM: Business Meeting

Location: Union Station A (North Building, 1st Floor)

Tuesday, October 15

7:30 AM – 5:00 PM: Registration

Location: Union Station Foyer (North Building, 1st Floor)

7:30 AM – 8:30 AM: Breakfast

Location: Union Station Foyer & Union Station C (North Building, 1st Floor)

8:30 AM – 9:30 AM: Keynote by Bill Dally

Increasing computing performance enables new applications and greater value from computing. With the end of Moore's Law and Dennard Scaling, continued performance scaling will come primarily from specialization. Specialized hardware engines can achieve performance and efficiency from 10x to 10,000x a CPU through specialization, parallelism, and optimized memory access. Graphics processing units are an ideal platform on which to build domain-specific accelerators. They provide very efficient, high performance communication and memory subsystems - which are needed by all domains. Specialization is provided via "cores", such as tensor cores that accelerate deep learning or ray-tracing cores that accelerate specific applications. This talk will describe some common characteristics of domain-specific accelerators via case studies.

Bill Dally is Chief Scientist and Senior Vice President of Research at NVIDIA Corporation and a Professor (Research) and former chair of Computer Science at Stanford University. Bill is currently working on developing hardware and software to accelerate demanding applications including machine learning, bioinformatics, and logical inference. He has a history of designing innovative and efficient experimental computing systems. While at Bell Labs Bill contributed to the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. At the Massachusetts Institute of Technology his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. At Stanford University his group developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations, the Merrimac supercomputer, which led to GPU computing, and the ELM low-power processor. Bill is a Member of the National Academy of Engineering, a Fellow of the IEEE, a Fellow of the ACM, and a Fellow of the American Academy of Arts and Sciences. He has received the ACM Eckert-Mauchly Award, the IEEE Seymour Cray Award, the ACM Maurice Wilkes award, the IEEE-CS Charles Babbage Award, and the IPSJ FUNAI Achievement Award. He currently leads projects on computer architecture, network architecture, circuit design, and programming systems. He has published over 250 papers in these areas, holds over 160 issued patents, and is an author of the textbooks, Digital Design: A Systems Approach, Digital Systems Engineering, and Principles and Practices of Interconnection Networks.

9:30 AM – 10:30 AM: Lightning Talks II

Location: Union Station B (North Building, 1st Floor)
Session Chair: Yuhao Zhu

10:30 AM – 11:00 AM: Coffee Break

Location: Union Station Foyer (North Building, 1st Floor)

11:00 AM – 12:00 PM

Session Chair: Prashant Nair
Distributed Logless Atomic Durability with Persistent Memory
Siddharth Gupta (EPFL); Alexandros Daglis (Georgia Tech); Babak Falsafi (EPFL)

SuperMem: Enabling Application-Transparent Secure Persistent Memory with Low Overheads
Pengfei Zuo (Huazhong University of Science and Technology & University of California, Santa Barbara); Yu Hua (Huazhong University of Science and Technology); Yuan Xie (University of California, Santa Barbara)

Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory
Congming Gao (University of Pittsburgh; Chongqing University); Min Ye (YEESTOR Microelectronics Co., Ltd); Qiao Li and Chun Jason Xue (City University of Hong Kong); Youtao Zhang (University of Pittsburgh); Liang Shi (East China Normal University); Jun Yang (University of Pittsburgh)
Session Chair: Trevor Carlson
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue
Hideki Ando (Nagoya University)

Towards the Adoption of Local Branch Predictors in Out-Of-Order Superscalar Processors
Niranjan Soundararajan, Saurabh Gupta, Ragavendra Natarajan (Intel Labs); Jared Stark, Rahul Pal, Franck Sala, Lihu Rappoport, Adi Yoaz (Intel); Sreenivas Subramoney (Intel Labs)

DSPatch: Dual Spatial Pattern Prefetcher
Rahul Bera (Intel Corp); Anant Nori (Intel); Onur Mutlu (ETH Zurich); Sreenivas Subramoney (Intel Labs)
Session Chair: Mengjia Yan
CHERIvoke: Pointer Revocation Using CHERI Capabilities for Temporal Memory Safety
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg (University of Cambridge); Peter G. Neumann (SRI International); Simon W. Moore, Robert N. M. Watson, Timothy M. Jones (University of Cambridge)

Practical Byte-Granular Memory Blacklisting Using Califorms
Hiroshi Sasaki, Miguel Arroyo, Mohamed Tarek Ibn Ziad (Columbia University); Koustubha Bhat (Vrije Universiteit Amsterdam); Kanad Sinha (Columbia University); Simha Sethumadhavan (Columbia University/Chip Scan)

NDA: Preventing Speculative Execution Attacks at Their Source
Ofir Weisse, Ian Neal, Kevin Loughlin, Thomas Wenisch, Baris Kasikci (University of Michigan)

12:00 PM – 1:30 PM: Awards Lunch

Location: George Bellows Ballroom (Hilton, lower level)

1:30 PM – 2:50 PM

Session Chair: Pradip Bose
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm
Wenqin Huangfu (University of California at Santa Barbara); Xueqi Li (Institute of Computing Technology, Chinese Academy of Sciences); Shuangchen Li, Xing Hu, Peng Gu (University of California, Santa Barbara); Yuan Xie (Univ. of California Santa Barbara)

SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations
Konstantinos Kanellopoulos (ETH Zurich); Christina Giannoula (National Technical University of Athens, ETH Zurich); Roknoddin AziziBarzoki and Nika Mansouri-Ghiasi (ETH Zurich); Nandita Vijaykumar (Carnegie Mellon University, ETH Zurich); Juan Gómez Luna, Taha Shahroodi, Skanda Koppula (ETH Zurich); Onur Mutlu (ETH Zurich, Carnegie Mellon University)

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach
Mingyu Yan (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences); Xing Hu, Shuangchen Li, Abanti Basak (University of California, Santa Barbara); Han Li (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences); Xin Ma and Itir Akgun (University of California, Santa Barbara); Yujing Feng (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences); Peng Gu and Lei Deng (University of California, Santa Barbara); Xiaochun Ye, Zhimin Zhang, Dongrui Fan (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences); Yuan Xie (University of California, Santa Barbara)

Best Paper Nominee
Tigris: Architecture and Algorithms for 3D Perception in Point Clouds
Tiancheng Xu, Boyuan Tian, Yuhao Zhu (University of Rochester)
Session Chair: Jack Wadden
ASV: Accelerated Stereo Vision System
Yu Feng (University of Rochester); Paul Whatmough (Arm Research); Yuhao Zhu (University of Rochester)

Distilling the Essence of Raw Video to Reduce Memory Usage and Energy at Edge Devices
Haibo Zhang, Shulin Zhao, Ashutosh Pattnaik, Mahmut Taylan Kandemir, Anand Sivasubramaniam, Chita Das (Penn State)

MANIC: A Vector-Dataflow Architecture for Ultra-Low-Power Embedded Systems
Graham Gobieski, Amolak Nagi, Nathan Serafin, Mehmet Meric Isgenc, Nathan Beckmann, Brandon Lucia (Carnegie Mellon University)

SOSA: Self-optimizing Learning with Self-adaptive Control for Hierarchical SoC Management
Bryan Donyanavard (University of California, Irvine); Armin Sadighi and Florian Maurer (Technische Universitat Munchen); Tiago Müaut;ck (University of California, Irvine); Amir Rahmani (University of California, Irvine and TU Wien); Andreas Herkersdorf (Technical University of Munich); Nikil Dutt (University of California, Irvine)
Session Chair: Jishen Zhao
NetDIMM: Low-Latency, Near-Memory Network Interface Architecture
Mohammad Alian (UIUC); Nam Sung Kim (Samsung/UIUC)

GraphQ: Scalable PIM-Based Graph Processing
Youwei Zhuo and Chao Wang (University of Southern California); Mingxing Zhang (Tsinghua University); Rui Wang (Beihang University); Dimin Niu (Alibaba Inc); Yanzhi Wang (Northeastern University); Xuehai Qian (University of Southern California)

Charon: Specialized Near-Memory Processing Architecture for Clearing Dead Objects in Memory
Jaeyoung Jang (Sungkyunkwan University); Jun Heo, Yejin Lee, Jaeyeon Won, Seonghak Kim, Sung Jun Jung (Seoul National University); Hakbeom Jang (Sungkyunkwan University); Tae Jun Ham and Jae W. Lee (Seoul National University)

TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning
Youngeun Kwon, Yunjae Lee, Minsoo Rhu (KAIST)

2:50 PM – 4:00 PM: SRC Finalist Presentations

Location: Union Station C (North Building, 1st Floor)

2:50 PM – 4:00 PM: Poster Session II & Coffee

Location: Union Station Foyer (North Building, 1st Floor)

4:00 PM – 5:20 PM

Session Chair: Bill Dally
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach
Hyoukjun Kwon and Prasanth Chatarasi (Georgia Tech); Michael Pellauer (Nvidia); Angshuman Parashar (NVIDIA); Vivek Sarkar (Georgia Institute of Technology); Tushar Krishna (Georgia Tech)

MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation
Lillian Pentecost and Marco Donato (Harvard University); Brandon Reagen (Facebook); Udit Gupta, Siming Ma, Gu-Yeon Wei, David Brooks (Harvard University)

Neuron-Level Fuzzy Memoization in RNNs
Franyell Silfa, Gem Dot, Jose Maria Arnau, Antonio Gonzalez (Polytechnic University of Catalonia)

Manna: An Accelerator for Memory-Augmented Neural Networks
Jacob R. Stevens and Ashish Ranjan (Purdue University); Dipankar Das and Bharat Kaul (Intel); Anand Raghunathan (Purdue University)
Session Chair: Saugata Ghose
Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability
Xiao Liu (University of California, San Diego); David Roberts (unaffiliated); Rachata Ausavarungnirun (King Mongkut's University of Technology North Bangkok and Carnegie Mellon University); Onur Mutlu (ETH Zurich); Jishen Zhao (University of California, San Diego)

Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support
Gagandeep Panwar, Da Zhang, Yihan Pang, Mai Dahshan (Virginia Tech); Nathan Debardeleben (Los Alamos National Laboratory); Binoy Ravindran and Xun Jian (Virginia Tech)

SSP: Eliminating Redundant Writes in Failure-Atomic NVRAMs via Shadow Sub-Paging
Yuanjiang Ni (University of California, Santa Cruz); Jishen Zhao (UCSD); Heiner Litz and Daniel Bittman (University of California, Santa Cruz); Ethan Miller (University of California, Santa Cruz / Pure Storage)

Towards Efficient NVDIMM-Based Heterogeneous Storage Hierarchy Management for Big Data Workloads
Renhai Chen (Tianjin University); Zili Shao (The Chinese University of Hong Kong); Duo Liu (Chongqing University); Zhiyong Feng (Tianjin University); Tao Li (University of Florida)
Session Chair: Daniel Sanchez
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor
Lucas Morais and Alfredo Goldman (University of Sao Paulo); Carlos Álvarez (Barcelona Supercomputing Center); Michael Frank (MagiCore Inc.); Jaume Bosch (Barcelona Supercomputing Center); Vitor Silva (University of Sao Paulo); Guido Araujo (Institute of Computing, University of Campinas)

SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution
Mayank Parasar (Georgia Tech); Joshua San Miguel (University of Wisconsin-Madison); Paul Gratz (Texas A&M University); Natalie Enright Jerger (University of Toronto); Tushar Krishna (Georgia Tech)

PUSh: Data Race Detection Based on Hardware-Supported Prevention of Unintended Sharing
Diyu Zhou and Yuval Tamir (UCLA)

EMI Architectural Model and Core Hopping
Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau (UC Santa Cruz)

6:00 PM – 9:00 PM: Excursion & Banquet at COSI

Departure: Buses leave from the Hilton (main entrance on N. High St.) at 5:30 PM and at 6:00 PM
Return: Buses leave from COSI starting at 8:30 PM

Wednesday, October 16

7:30 AM – 8:30 AM: Breakfast

Location: Union Station Foyer & Union Station C (North Building, 1st Floor)

8:30 AM – 9:30 AM: Keynote by Lynn Conway

In 2015, US Chief Technology Officer Megan Smith raised profound questions about women's contributions in science, engineering and math being erased from history. In this talk we explore a case study of such erasure and surface a very counterintuitive conjecture about the underlying causes and effects.

For more information, please refer to "The Disappeared: Beyond Winning and Losing", which appeared in IEEE Computer in October 2018.

After earning her BS and MSEE from Columbia University, Lynn joined IBM Research in 1964, where she made foundational contributions to computer architecture. Fired by IBM as she underwent gender transition in 1968, Lynn started her career all over again in 'stealth mode'.

Joining Xerox Palo Alto Research Center in 1973, Lynn invented scalable MOS design rules and simplified methods for silicon chip design, was principal author of the famous 'Mead-Conway' text, and pioneered the teaching of these methods at MIT — launching a world-wide revolution in VLSI microelectronic system design in the late 1970s. Lynn also invented an ARPAnet based e-commerce infrastructure for rapid chip-prototyping in 1979, spawning the modern "fabless design" plus "silicon foundry" industry model for semiconductor design and manufacturing. Lynn joined the University of Michigan in 1985 as Professor of EECS and Associate Dean of Engineering, where she continued her distinguished career.

A Fellow of the IEEE and the AAAS, Lynn has won many awards for her contributions including the Computer Pioneer Award of the IEEE Computer Society, Wetherill Medal of the Franklin Institute, induction into the Computer History Museum's Hall of Fellows, election to the National Academy of Engineering, and four honorary doctorates. Awarded the 2015 James Clerk Maxwell Medal by the IEEE and the Royal Society of Edinburgh, her citation included these words: "Lynn Conway's work has provided the underpinnings for innovations, discoveries and achievements in every area of scientific and humanitarian study."

9:35 AM – 10:35 AM

Session Chair: Sophia Shao
μIR - An Intermediate Representation for Transforming and Optimizing the Microarchitecture of Application Accelerators
Amirali Sharifian, Reza Hojabr, Navid Rahimi (SFU); Sihao Liu (UCLA); Apala Guha (SFU); Tony Nowatzki (UCLA); Arrvindh Shriraman (SFU)

Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms
Vidushi Dadu and Jian Weng (UCLA); Sihao Liu (Xi'an Jiaotong University); Tony Nowatzki (UCLA)

Best Paper Nominee
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
Zhaoshi Li, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, Shaojun Wei (Tsinghua University)
Session Chair: Miezko Lis
Best Paper Winner
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
Jiyong Yu and Mengjia Yan (University of Illinois at Urbana-Champaign); Artem Khyzha and Adam Morrison (Tel Aviv University); Josep Torrellas and Christopher Fletcher (University of Illinois at Urbana-Champaign)

LATCH: A Locality-Aware Taint CHecker
Daniel Townley (Binghamton University); Khaled Khasawneh (University of California Riverside); Dmitry Ponomarev (State Univeristy of New York at Binghamton); Nael Abu-Ghazaleh (University of California Riverside); Lei Yu (Binghamton University)

EMMA: Hardware/Software Attestation Framework for Embedded Systems using Electromagnetic Signals
Nader Sehatbakhsh, Alireza Nazari, Haider Khan, Alenka Zajic, Milos Prvulovic (Georgia Tech)

10:35 AM – 11:00 AM: Coffee Break

Location: Union Station Foyer (North Building, 1st Floor)

11:00 AM – 12:00 PM

Session Chair: José Joao
Temporal Prefetching Without the Off-Chip Metadata
Hao Wu (UT Austin); Akanksha Jain and Calvin Lin (University of Texas at Austin); Krishnendra Nathella and Joseph Pusdesris (Arm); Dam Sunwoo (Arm Research)

PHI: Architectural Support for Synchronization- and Bandwidth-Efficient Commutative Scatter Updates
Anurag Mukkara (MIT); Nathan Beckmann (CMU); Daniel Sanchez (MIT)

Prefetched Address Translation
Artemiy Margaritov (University of Edinburgh); Dmitrii Ustiugov and Edouard Bugnion (EPFL); Boris Grot (University of Edinburgh)
Session Chair: Arrvindh Shriraman
Best Paper Nominee
Directed Statistical Warming Through Time Traveling
Nikos Nikoleris (Arm Research); Lieven Eeckhout (Ghent University); Erik Hagersten (Uppsala University); Trevor E. Carlson (National University of Singapore)

Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection
Donggyu Kim, Jerry Zhao, Jonathan Bachrach, Krste Asanovic (University of California Berkeley)

Architectural Implications of Function-as-a-Service Computing
Mohammad Shahrad, Jonathan Balkind, David Wentzlaff (Princeton University)

12:00 PM – 12:15 PM: Best Paper Award & Closing Remarks

Location: Union Station B (North Building, 1st Floor)

1:00 PM – 6:30 PM: US Air Force Museum Excursion

Departure: Buses leave from the Hilton (main entrance on N. High St.) at 1:00 PM
Return: Buses leave from the museum at 5:00 PM