List of Eligible Papers for the 2018 Award

View the 2018 call for nominations.

MICRO 1996

Paper Title	Authors
A Persistent Rescheduled-Page Cache for Low Overhead Object Code Compatibility in VLIW Architectures	Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
Integrating a Misprediction Recovery Cache (MRC) Into a Superscalar Pipeline	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta
Accurate and Practical Profile-Driven Compilation Using the Profile Buffer	Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
Efficient Path Profiling	Thomas Ball, James R. Larus
Profile-Driven Instruction Level Parallel Scheduling with Application to Super Blocks	C. Chekuri, R. Johnson, R. Motwani, B. Natarajan, B. R. Rau, M. Schlansker
Speculative Hedge: Regulating Compile-Time Speculation Against Profile Variations	Brian L. Deitrich, Wen-mei W. Hwu
Hot Cold Optimization of Large Windows/NT Applications	Robert Cohn, P. Geoffrey Lowney
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results	Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu
Analysis Techniques for Predicated Code	Richard Johnson, Michael Schlansker
Global Predicate Analysis and Its Application to Register Allocation	David M. Gillies, Dz-ching Roy Ju, Richard Johnson, Michael Schlansker
Modulo Scheduling of Loops in Control-Intensive Non-Numeric Programs	Daniel M. Lavery, Wen-mei W. Hwu
Assigning Confidence to Conditional Branch Predictions	Erik Jacobsen, Eric Rotenberg, J. E. Smith
Compiler Synthesized Dynamic Branch Prediction	Scott Mahlke, Balas Natarajan
Wrong-Path Instruction Prefetching	Jim Pierce, Trevor Mudge
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture	Robert Yung
Increasing the Instruction Fetch Rate Via Block-Structured Instruction Set Architectures	Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors	Shlomit S. Pinter, Adi Yoaz
The Performance Potential of Data Dependence Speculation & Collapsing	Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith
Heuristics for Register-Constrained Software Pipelining	Josep Llosa, Mateo Valero, Eduard Ayguadé
Software Pipelining Loops with Conditional Branches	Mark G. Stoodley, Corinna G. Lee
Combining Loop Transformations Considering Caches and Scheduling	Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen
Instruction Scheduling and Executable Editing	Eric Schnarr, James R. Larus
Instruction Scheduling for the HP PA-8000	David A. Dunn, Wei-Chung Hsu
Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries	Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich
Custom-Fit Processors: Letting Applications Define Architectures	Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli
Optimization for a Superscalar Out-of-Order Machine	Anne M. Holler
Optimization of Machine Descriptions for Efficient Use	John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramabriohna Rau

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MICRO 1997

Paper Title	Authors
The Bi-Mode Branch Predictor	Chih-Chieh Lee, I-Cheng K. Chen, Trevor N. Mudge
Path-Based Next Trace Prediction	Quinn Jacobson, Eric Rotenberg, James E. Smith
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism	Daniel Holmes Friendly, Sanjay Jeram Patel, Yale N. Patt
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions Into the Reservation Stations Out-of-Order	Jared Stark, Paul Racunas, Yale N. Patt
On High-Bandwidth Data Cache Design for Multi-Issue Processors	Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
Run-Time Spatial Locality Detection and Optimization	Teresa L. Johnson, Matthew C. Merten, Wen-Mei W. Hwu
A Comparison of Data Prefetching On an Access Decoupled and Superscalar Machine	G. P. Jones, N. P. Topham
The Design and Performance of a Conflict-Avoiding Cache	Nigel Topham, Antonio González, José González
Prediction Caches for Superscalar Processors	James E. Bennett, Michael J. Flynn
A Framework for Balancing Control Flow and Predication	David I. August, Wen-mei W. Hwu, Scott A. Mahlke
Evaluation of Scheduling Techniques On a SPARC-Based VLIW Testbed	Seongbae Park, SangMin Shim, Soo-Mook Moon
Tuning Compiler Optimizations for Simultaneous Multithreading	Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen
Exploiting Dead Value Information	Milo M. Martin, Amir Roth, Charles N. Fischer
Trace Processors	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, Jim Smith
The Multicluster Architecture: Reducing Cycle Time Through Partitioning	Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko Vranesic
Out-of-Order Vector Architectures	Roger Espasa, Mateo Valero, James E. Smith
Initial Results On the Performance and Cost of Vector Microprocessors	Corinna G. Lee, Derek J. DeVries
The Filter Cache: An Energy Efficient Memory Structure	Johnson Kin, Munish Gupta, William H. Mangione-Smith
Improving Code Density Using Compression Techniques	Charles Lefurgy, Peter Bird, I-Cheng Chen, Trevor Mudge
Procedure Based Program Compression	Darko Kirovski, Johnson Kin, William H. Mangione-Smith
Improving the Accuracy and Performance of Memory Communication Through Renaming	Gary S. Tyson, Todd M. Austin
Microarchitecture Support for Improving the Performance of Load Target Prediction	Chung-Ho Chen, Akida Wu
Streamlining Inter-Operation Memory Communication Via Data Dependence Prediction	Andreas Moshovos, Gurindar S. Sohi
The Predictability of Data Values	Yiannakis Sazeides, James E. Smith
Value Profiling	Brad Calder, Peter Feller, Alan Eustace
Can Program Profiling Support Value Prediction?	Freddy Gabbay, Avi Mendelson
Highly Accurate Data Value Prediction Using Hybrid Predictors	Kai Wang, Manoj Franklin
ProfileMe: Hardware Support for Instruction-Level Profiling On Out-of-Order Processors	Jeffrey Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl, George Chrysos
Procedure Placement Using Temporal Ordering Information	Nikolas Gloy, Trevor Blackwell, Michael D. Smith, Brad Calder
Predicting Data Cache Misses in Non-Numeric Applications Through Correlation Profiling	Todd C. Mowry, Chi-Keung Luk
Available Parallelism in Video Applications	Heng Liao, Andrew Wolfe
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems	Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
Cache Sensitive Modulo Scheduling	F. Jesús Sánchez, Antonio González
Unroll-and-Jam Using Uniformly Generated Sets	Steve Carr, Yiping Guan
Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization	Rajiv Gupta, David A. Berson, Jesse Z. Fang

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MICRO 1998

Paper Title	Authors
A Bandwidth-Efficient Architecture for Media Processing	Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
Simple Vector Microprocessors for Multimedia Applications	Corinna G. Lee, Mark G. Stoodley
Evaluating MMX Technology Using DSP and Multimedia Applications	Ravi Bhargava, Lizy K. John, Brian L. Evans, Ramesh Radhakrishnan
Analyzing the Working Set Characteristics of Branch Execution	Sangwook P. Kim, Gary S. Tyson
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes	Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan
The YAGS Branch Prediction Scheme	Avinoam N. Eden, Trevor Mudge
Task Selection for a Multiscalar Processor	T. N. Vijaykumar, Gurindar S. Sohi
Split-Path Enhanced Pipeline Scheduling for Loops with Control Flows	SangMin Shim, Soo-Mook Moon
Effective Cluster Assignment for Modulo Scheduling	Erik Nystrom, Alexandre E. Eichenberger
Better Global Scheduling Using Path Profiles	Cliff Young, Michael D. Smith
Predictive Techniques for Aggressive Load Speculation	Glenn Reinman, Brad Calder
Compiler-Directed Early Load-Address Generation	Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu
Load Latency Tolerance in Dynamically Scheduled Processors	Srikanth T. Srinivasan, Alvin R. Lebeck
Improving I/O Performance with a Conditional Store Buffer	Lambert Schaelicke, Al Davis
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors	Daniel Holmes Friendly, Sanjay Jeram Patel, Yale N. Patt
Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors	Chi-Keung Luk, Todd C. Mowry
Code Compression Based on Operand Factorization	Guido Araujo, Paulo Centoducatte, Mario Cartes, Ricardo Pannain
Understanding the Differences Between Value Prediction and Instruction Reuse	Avinash Sodani, Gurindar S. Sohi
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification	Stephen Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz
A Dynamic Multithreading Processor	Haitham Akkary, Michael A. Driscoll
Widening Resources: A Cost-Effective Technique for Aggressive ILP Architectures	David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
The Cascaded Predictor: Economical and Adaptive Branch Target Prediction	Karel Driesen, Urs Hölzle
Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms	Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark
Predicting Indirect Branches via Data Compression	John Kalamatianos, David R. Kaeli
Improving Locality Using Loop and Data Transformations in an Integrated Framework	Mahmut Kandemir, Alok Choudhary, J. Ramanujam, Prithviraj Banerjee
Precise Register Allocation for Irregular Architectures	Timothy Kong, Kent D. Wilken
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures	Emre Özer, Sanjeev Banerjia, Thomas M. Conte

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MICRO 1999

Paper Title	Authors
Control Independence in Trace Processors	Eric Rotenberg, James E. Smith
Fetch Directed Instruction Prefetching	Glenn Reinman, Brad Calder, Todd M. Austin
Improving Branch Predictors by Correlating on Data Values	Timothy H. Heil, Zak Smith, James E. Smith
Instruction Fetch Mechanisms for Multipath Execution Processors	Artur Klauser, Dirk Grunwald
A Superscalar 3D Graphics Engine	Andrew Wolfe, Derek B. Noonburg
Dynamic 3D Graphics Workload Characterization and the Architectural Implications	Tulika Mitra, Tzi-cker Chiueh
Exploiting a New Level of DLP in Multimedia Applications	Jesus Corbal, Roger Espasa, Mateo Valero
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors	Sergei Y. Larin, Thomas M. Conte
Evaluation of a High Performance Code Compression Method	Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops	Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends
Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems	Santosh G. Abraham, Scott A. Mahlke
Hardware Identification of Cache Conflict Misses	Jamison D. Collins, Dean M. Tullsen
Access Region Locality for High-Bandwidth Processor Memory System Design	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
Code Transformations to Improve Memory Parallelism	Vijay S. Pai, Sarita V. Adve
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results	Daniel A. Connors, Wen-mei W. Hwu
Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing	Soner Onder, Rajiv Gupta
Read-After-Read Memory Dependence Prediction	Andreas Moshovos, Gurindar S. Sohi
Delaying Physical Register Allocation through Virtual-Physical Registers	Teresa Monreal, Antonio González, Mateo Valero, José González, Victor Viñals
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design	Todd M. Austin
Exploiting ILP in Page-based Intelligent Memory	Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra
The Use of Multithreading for Exception Handling	Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
Value Prediction for Speculative Multithreaded Architectures	Pedro Marcuello, Jordi Tubella, Antonio González
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors	Enric Musoll
Selective Cache Ways: On-Demand Cache Resource Allocation	David H. Albonesi
Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs	Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks	Alexandre E. Eichenberger, Waleed Meleis
Optimizations and Oracle Parallelism with Dynamic Translation	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind

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MICRO 2000

Paper Title	Authors
Eager Writeback - A Technique for Improving Bandwidth Utilization	Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Silent Stores for Free	Kevin M. Lepak, Mikko H. Lipasti
A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality	Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
Predictor-Directed Stream Buffers	Timothy Sherwood, Suleyman Sair, Brad Calder
On Pipelining Dynamic Instruction Scheduling Logic	Jared Stark, Mary D. Brown, Yale N. Patt
The Impact of Delay on the Design of Branch Predictors	Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin
Improving BTB Performance in the Presence of DLLs	Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
Efficient Checker Processor Design	Saugata Chatterjee, Christopher T. Weaver, Todd M. Austin
An Integrated Approach to Accelerate Data and Predicate Computations in Hyperblocks	Alexandre E. Eichenberger, Waleed Meleis, Suman Maradani
Accurate and Efficient Predicate Analysis with Binary Decision Diagrams	John W. Sias, Wen-mei W. Hwu, David I. August
Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture	F. Jesús Sánchez, Antonio González
Two-Level Hierarchical Register File Organization for VLIW Processors	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
PipeRench Implementation of the Instruction Path Coprocessor	Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
Efficient Conditional Operations for Data-Parallel Architectures	Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
Flexible Hardware Acceleration for Multimedia Oriented Microprocessors	Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man
Very Low Power Pipelines Using Significance Compression	Ramon Canal, Antonio González, James E. Smith
A Static Power Model for Architects	J. Adam Butts, Gurindar S. Sohi
A Framework for Dynamic Energy Efficiency and Temperature Management	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
Dynamic Zero Compression for Cache Energy Reduction	Luis Villa, Michael Zhang, Krste Asanovic
Register Integration: A Simple and Efficient Implementation of Squash Reuse	Amir Roth, Gurindar S. Sohi
The Store-Load Address Table and Speculative Register Promotion	Matt Postiff, David A. Greene, Trevor N. Mudge
Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Frequent Value Compression in Data Caches	Jun Yang, Youtao Zhang, Rajiv Gupta
A Study of Slipstream Processors	Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
Relational Profiling: Enabling Thread-Level Parallelism in Virtual Machines	Timothy H. Heil, James E. Smith
Calpa: A Tool for Automating Selective Dynamic Compilation	Markus Mock, Craig Chambers, Susan J. Eggers
Increasing the Size of Atomic Instruction Blocks Using Control Flow Assertions	Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum
Reducing Wire Delay Penalty Through Value Prediction	Joan-Manuel Parcerisa, Antonio González
Compiler Controlled Value Prediction Using Branch Predictor Based Confidence	Eric Larson, Todd M. Austin
Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors	Amirali Baniasadi, Andreas Moshovos
Performance Improvement with Circuit-Level Speculation	Tong Liu, Shih-Lien Lu

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