| Vacuum Packing – Extracting Hardware-Detected Program Phases for Post-Link Optimization | Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten, Wen-mei W. Hwu |
| Power Protocol – Reducing Power Dissipation on Off-Chip Data Buses | K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir |
| Hierarchical Scheduling Windows | Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, Bryan Black |
| Characterizing and Predicting Value Degree of Use | J. Adam Butts, Gurindar S. Sohi |
| Microarchitectural Support for Precomputation Microthreads | Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt |
| Pointer Cache Assisted Prefetching | Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen |
| Three-Dimensional Memory Vectorization for High Bandwidth Media Memory Systems | Jesús Corbal, Roger Espasa, Mateo Valero |
| DELI – A New Run-Time Control Point | Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Joseph A. Fisher |
| Managing Static Leakage Energy in Microprocessor Functional Units | Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman |
| A Faster Optimal Register Allocator | Changqing Fu, Kent D. Wilken |
| Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor | Enric Gibert, F. Jesús Sánchez, Antonio González |
| Microarchitectural Denial of Service – Insuring Microarchitectural Fairness | Dirk Grunwald, Soraya Ghiasi |
| Dynamic Addressing Memory Arrays with Physical Locality | Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai |
| Generating Physical Addresses Directly for Saving Instruction TLB Energy | Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen |
| Drowsy Instruction Caches – Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-Bank Prediction | Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge |
| Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks | Christoforos E. Kozyrakis, David A. Patterson |
| Compiling for Instruction Cache Performance on a Multithreaded Architecture | Rakesh Kumar, Dean M. Tullsen |
| Convergent Scheduling | Walter Lee, Diego Puppin, Shane Swenson, Saman P. Amarasinghe |
| Reduced Code Size Modulo Scheduling in the Absence of Hardware Support | Josep Llosa, Stefan M. Freudenberger |
| Exploiting Data-Width Locality to Increase Superscalar Execution Handwidth | Gabriel H. Loh |
| Cherry – Checkpointed Early Resource Recycling in Out-of-Order Microprocessors | José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas |
| Instruction Fetch Deferral Using Static Slack | Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta |
| Reducing Register Ports for Higher Speed and Lower Energy | Il Park, Michael D. Powell, T. N. Vijaykumar |
| Three Extensions to Register Integration | Vlad Petric, Anne Bracy, Amir Roth |
| Fetching Instruction Streams | Alex Ramírez, Oliverio J. Santana, Josep-Lluís Larriba-Pey, Mateo Valero |
| A Quantitative Framework for Automated Pre-Execution Thread Selection | Amir Roth, Gurindar S. Sohi |
| Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture | Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott |
| Register Write Specialization Register Read Specialization – A Path to Complexity-Effective Wide-Issue Superscalar Processors | André Seznec, Eric Toullec, Olivier Rochecouste |
| Optimizing Pipelines for Power and Performance | Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma |
| Using Modern Graphics Architectures for General-Purpose Computing – A Framework and Analysis | Chris J. Thompson, Sahngyun Hahn, Mark Oskin |
| Microarchitectural Exploration with Liberty | Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, David I. August |
| Orion – A Power-Performance Simulator for Interconnection Networks | Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik |
| Compiler Managed Micro-Cache Bypassing for High Performance EPIC Processors | Youfeng Wu, Ryan N. Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang |
| Energy Efficient Frequent Value Data Cache Design | Jun Yang, Rajiv Gupta |
| Compiler-Directed Instruction Cache Leakage Optimization | Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
| Master/Slave Speculative Parallelization | Craig B. Zilles, Gurindar S. Sohi |
